MEMS cavity with non-contaminating seal
A semiconductor device includes a first silicon layer disposed between second and third silicon layers and separated therefrom by respective first and second oxide layers. A cavity within the first silicon layer is bounded by interior surfaces of the second and third silicon layers, and a passageway extends through the second silicon layer to enable material removal from within the semiconductor device to form the cavity. A metal feature is disposed within the passageway to hermetically seal the cavity.
1. An integrated circuit comprising:
a layer stack, the layer stack comprising a substrate and a lid, at least one of the substrate and the lid having one or more layers of crystal silicon;
a chamber within the layer stack, between the substrate and the lid;
a microelectromechanical systems (MEMS) resonator within the chamber, the MEMS resonator having a piezoelectric layer and first and second electrodes, one of the first and second electrodes to provide electrical stimulus to the piezoelectric layer to excite motion of the MEMS resonator and one of the first and second electrodes to provide an output signal representing frequency of motion of the MEMS resonator;
conductive paths extending between the first and second electrodes and respective contacts on an exterior surface of the integrated circuit;
a passageway extending through the one or more layers of crystal silicon;
a sealant feature that seals the passageway relative to the one or more layers of crystal silicon, the chamber also being hermitically sealed relative to an exterior surface of the integrated circuit, the sealant feature characterized by use of low temperature deposition process that causes the sealant feature to completely plug the passageway at a location adjacent a first side of the one or more layers of crystal silicon but to not penetrate to and not occlude the passageway adjacent a second side of the one or more layers of crystal silicon that is closest to the chamber.
2. The integrated circuit of claim 1 wherein the sealant feature comprises a non-metal.
3. The integrated circuit of claim 2 wherein the sealant feature comprises epitaxial silicon.
4. The integrated circuit of claim 1 wherein the sealant feature comprises a metal.
5. The integrated circuit of claim 4 wherein the metal is tungsten.
6. The integrated circuit of claim 1 wherein the passageway has at least one bend, such that a line of sight path does not exist through the one or more layers of crystal silicon.
7. The integrated circuit of claim 1 wherein the passageway is characterized by an aspect ratio of length of the passageway along a direction that is perpendicular to the layer stack to a minimum width of the passageway that is equal to five or more, and wherein the minimum width of the passageway is less than or equal to two microns.
8. The integrated circuit of claim 1 further comprising an oxide layer that encapsulates the sealant feature relative to an exterior of the integrated circuit.
9. The integrated circuit of claim 1 wherein the electrodes are configured to sense flexure mode frequency of motion of the MEMS resonator.
10. The integrated circuit of claim 1 wherein at least one of the first and second electrodes comprises crystal silicon that is degenerately doped with an N-type impurity.
11. The integrated circuit of claim 10 wherein a first one of the first and second electrodes predominantly comprises single crystal silicon and a second one of the first and second electrodes predominantly comprises polycrystal silicon.
12. An integrated circuit comprising:
electrical contacts on an exterior surface of the integrated circuit;
a layer stack, the layer stack comprising a substrate and a lid, at least one of the substrate and the lid having one or more layers of crystal silicon;
a chamber within the layer stack, between the substrate and the lid;
a microelectromechanical systems (MEMS) resonator within the chamber, the MEMS resonator having a piezoelectric layer and first and second electrodes, one of the first and second electrodes to provide electrical stimulus to the piezoelectric layer to excite motion of the MEMS resonator and one of the first and second electrodes to provide an output signal representing frequency of motion of the MEMS resonator, wherein further, at least one layer of the MEMS resonator predominantly comprises silicon that has been degenerately doped with an N-type impurity;
conductive paths extending between the first and second electrodes and respective ones of the contacts on the exterior surface of the integrated circuit;
a passageway extending through the one or more layers of crystal silicon;
a sealant feature that seals the passageway relative to the one or more layers of crystal silicon, the chamber also being hermitically sealed relative to an exterior surface of the integrated circuit, the sealant feature characterized by use of low temperature deposition process that causes the sealant feature to completely plug the passageway at a location adjacent a first side of the one or more layers of crystal silicon but to not penetrate to and not occlude the passageway adjacent a second side of the one or more layers of crystal silicon that is closest to the chamber.
13. The integrated circuit of claim 12 wherein the sealant feature predominantly comprises a non-metal.
14. The integrated circuit of claim 13 wherein the sealant feature predominantly comprises epitaxial silicon.
15. The integrated circuit of claim 12 wherein the sealant feature predominantly comprises a sputtered metal from the group of tungsten, copper, and aluminum.
16. The integrated circuit of claim 12 wherein the passageway has at least one bend, such that a line of sight path does not exist through the one or more layers of crystal silicon.
17. The integrated circuit of claim 12 wherein the passageway is characterized by an aspect ratio of length of the passageway along a direction that is perpendicular to the layer stack to a minimum width of the passageway that is equal to five or more, and wherein the minimum width of the passageway is less than or equal to two microns.
18. The integrated circuit of claim 12 further comprising an oxide layer that encapsulates the sealant feature relative to an exterior of the integrated circuit.
19. The integrated circuit of claim 12 wherein each of the first and second electrodes comprises crystal silicon that is degenerately doped with an N-type impurity.
20. The integrated circuit of claim 19 , wherein a first one of the first and second electrodes predominantly comprises single crystal silicon and a second one of the first and second electrodes predominantly comprises polycrystal silicon.