LIN communication circuit and a method of communicating between LIN busses
In aspects, a Local Interconnect Network (LIN) communication circuit including a first LIN master associated with a first LIN bus and a second LIN master associated with a second LIN bus is disclosed. A data link is connected between the first and second LIN masters. A first mirroring client is established at the first LIN master for receiving message bits corresponding to a LIN message in a first slot on the first LIN bus and for transmitting the message bits bitwise over the data link. A second mirroring client is established at the second LIN master for receiving the message bits and transmitting them over the second LIN bus. The first and second LIN masters include synchronised schedule tables such that the message bits on the second LIN bus are transmitted in a corresponding slot to the first.
1. A Local Interconnect Network (LIN) communication circuit comprising:
a first LIN master associated with a first LIN bus;
a second LIN master associated with a second LIN bus;
a data link connecting between the first and second LIN masters;
a first mirroring client established at the first LIN master for receiving message bits corresponding to a LIN message in a first slot on the first LIN bus and transmitting the message bits bitwise over the data link; and
a second mirroring client established at the second LIN master for receiving the message bits from the data link and transmitting the message bits over the second LIN bus, wherein the first and second LIN masters comprise first and second schedule tables respectively, and wherein the first and second schedule tables are synchronised such that the message bits transmitted on the second LIN bus are transmitted in a first slot on the second LIN bus corresponding to the first slot on the first LIN bus, the second schedule table adjusted such that at least one of a jitter or an inter-byte space is adjusted based on a LIN specification.
2. A LIN communication circuit according to claim 1 , further comprising a synchroniser for synchronising the first and second schedule tables, the second schedule table is adjusted to specify a jitter time for the first slot on the second LIN bus which is longer than a jitter time for the first slot specified in the first schedule table.
3. A LIN communication circuit according to claim 1 , wherein the second schedule table is adjusted to specify an inter-byte space for the first slot on the second LIN bus which is longer than an inter-byte space specified for the first slot in the first schedule table.
4. A LIN communication circuit according to claim 1 , further comprising a synchronisation link connecting between the first and second LIN masters for conveying schedule data for synchronising the first and second schedule tables.
5. A LIN communication circuit according to claim 1 , further comprising a first LIN slave node connected to the first LIN bus for transmitting the LIN message in the first slot in response to a message header in the first slot from the first LIN master.
6. A LIN communication circuit according to claim 1 , further comprising a second LIN slave node connected to the second LIN bus for receiving the LIN message in the first slot on the second LIN bus.
7. A LIN communication circuit according to claim 1 , wherein at least one of the first and second LIN masters are Electronic Control Units.
8. A method of communicating between LIN busses, the method comprising:
establishing a first mirroring client at a first LIN master associated with a first LIN bus;
establishing a second mirroring client at a second LIN master associated with a second LIN bus;
receiving, by the first mirroring client, message bits corresponding to a LIN message in a first slot on the first LIN bus and transmitting the message bits bitwise over a data link connecting between the first and second LIN masters; and
receiving, by the second mirror client, the message bits from the data link and transmitting the message bits over the second LIN bus, wherein the first and second LIN masters comprise first and second schedule tables respectively, and wherein the first and second schedule tables are synchronised such that the message bits transmitted on the second LIN bus are transmitted in a first slot on the second LIN bus corresponding to the first slot on the first LIN bus, the second schedule table adjusted such that at least one of a jitter or an inter-byte space is adjusted based on a LIN specification.
9. The method according to claim 8 , wherein a jitter time specified in the second schedule table for the first slot on the second LIN bus is longer than a jitter time specified in the first schedule table for the first slot.
10. The method according to claim 9 , wherein the jitter time specified in the second schedule table for the first slot on the second LIN bus is a maximum defined jitter.
11. The method according to claim 8 , wherein an inter-byte space specified in the second schedule table for the first slot on the second LIN bus is longer than an inter-byte space specified in the first schedule table for the first slot.
12. The method according to claim 8 , further comprising:
transmitting a message header in the first slot from the first LIN master, the message header identifying a first LIN slave node; and
transmitting the LIN message in the first slot from the first LIN slave node in response to the message header.
13. The method according to claim 8 , further comprising:
transmitting a corresponding message header in the first slot on the second LIN bus from the second LIN master, the corresponding message header identifying a first LIN slave node, transmitting the message bits over the second LIN bus comprises transmitting the LIN message from the second mirror client in the first slot on the second LIN bus.
14. The method according to claim 8 , wherein the step of transmitting the message bits bitwise over the data link comprises bitwise slicing the LIN message by the first mirroring client, and multiplexing the sliced bits with other data.
15. The method according to claim 8 , further comprising:
generating, by a virtual LIN slave node on the first LIN master, the message bits corresponding to the LIN message in a first slot on the first LIN bus.
16. A Local Interconnect Network (LIN) communication circuit comprising:
a first LIN master associated with a first LIN bus;
a second LIN master associated with a second LIN bus;
a data link connecting between the first and second LIN masters;
a first mirroring client established at the first LIN master for receiving message bits corresponding to a LIN message in a first slot on the first LIN bus and transmitting the message bits bitwise over the data link;
a second mirroring client established at the second LIN master for receiving the message bits from the data link and transmitting the message bits over the second LIN bus, wherein the first and second LIN masters comprise first and second schedule tables respectively; and
a synchroniser for synchronising the first and second schedule tables such that the message bits transmitted on the second LIN bus are transmitted in a first slot on the second LIN bus corresponding to the first slot on the first LIN bus, the second schedule table adjusted to specify a jitter time for the first slot which is longer than a jitter time for the first slot specified in the first schedule table.
17. A LIN communication circuit according to claim 16 , further comprising a synchronisation link connecting between the first and second LIN masters for conveying schedule data for synchronising the first and second schedule tables.
18. A LIN communication circuit according to claim 16 , further comprising a first LIN slave node connected to the first LIN bus for transmitting the LIN message in the first slot in response to a message header in the first slot from the first LIN master.
19. A LIN communication circuit according to claim 16 , further comprising a second LIN slave node connected to the second LIN bus for receiving the LIN message in the first slot on the second LIN bus.
20. A LIN communication circuit according to claim 16 , wherein at least one of the first and second LIN masters are Electronic Control Units.