Technologies for performing macro operations in memory

1. A memory comprising:

media access circuitry connected to a memory media, the media access circuitry configured to perform in-memory macro operations, each in-memory macro operation associated with a set of multiple in-memory operations to be performed on data present in the memory media, wherein the media access circuitry is to:

receive a single request to perform an in-memory macro operation;

determine the set of multiple in-memory operations associated with the in-memory macro operation based on the single request; and

perform, in response to the single request, the set of multiple in-memory operations associated with the in-memory macro operation on data present in the memory media, wherein the media access circuitry is further to provide, to a component of a compute device in which the memory is located, status data indicating that the in-memory macro operation is in progress.

2. The memory of claim 1 , wherein the media access circuitry is further to:

determine whether performance of the in-memory macro operation is complete; and

provide, in response to a determination that performance of the in-memory macro operation is complete, status data indicating that the in-memory macro operation is complete.

3. The memory of claim 1 , wherein to provide the status data the media access circuitry is further to write the status data to a register that is accessible by the component of the compute device.

4. The memory of claim 1 , wherein the single request indicates a location in the memory media of data on which to perform the set of multiple in-memory operations associated with the in-memory macro operation.

5. The memory of claim 1 , wherein the single request indicates a location in the memory media where a result of the in-memory macro operation is to be written.

6. The memory of claim 1 , wherein the in-memory macro operation is associated with a set of multiple in-memory compute operations.

7. The memory of claim 1 , wherein the in-memory macro operation is associated with a set of multiple artificial intelligence related operations.

8. The memory of claim 1 , wherein the in-memory macro operation is associated with a set of multiple in-memory operations on matrix data present in the memory media.

9. The memory of claim 1 , wherein the in-memory macro operation associated with the set of in-memory operations includes in-memory operations to any one or more of:

multiply matrices, convolve a matrix with a filter, any of add or subtract matrices, any of add, subtract, multiply, or divide a matrix with a constant, perform a matrix transpose, apply an activation function to a matrix, apply a pooling function to a matrix, apply a transcendental function to a matrix, perform batch normalization, determine an inner-product of vectors, determine an outer-product of vectors, any of read or write a matrix in column major format, and any of read or write a matrix in row major format.

10. The memory of claim 1 , wherein the media access circuitry is formed from a complementary metal-oxide-semiconductor.

11. The memory of claim 1 , wherein the memory media has a cross point architecture.

12. The memory of claim 11 , wherein the memory media has a three dimensional cross point architecture.

13. A method comprising:

receiving, by media access circuitry connected to a memory media, the media access circuitry configured to perform in-memory macro operations, each in-memory macro operation associated with a set of multiple in-memory operations to be performed on data present in the memory media, a single request to perform an in-memory macro operation;

determining, in response to the request and by the media access circuitry, the set of multiple in-memory operations associated with the in-memory macro operation based on the single request; and

performing, in response to the single request and by the media access circuitry, the set of multiple in-memory operations associated with the in-memory macro operation on data present in the memory media, wherein performing further comprises providing, to a component of a compute device in which the media access circuitry is located, status data indicating that the in-memory macro operation is in progress.

14. The method of claim 13 , further comprising:

determining, by the media access circuitry, whether performance of the in-memory macro operation is complete; and

providing, by the media access circuitry and in response to a determination that performance of the in-memory macro operation is complete, status data indicating that the in-memory macro operation is complete.

15. The method of claim 13 , wherein providing the status data comprises writing the status data to a register that is accessible by the component of the compute device.

16. The method of claim 13 , wherein the single request indicates a location in the memory media of data on which to perform the set of multiple in-memory operations indicated by the in-memory macro operation.

17. One or more non-transitory machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause media access circuitry connected to a memory media to:

configure the media access circuitry to associate a set of multiple in-memory operations with an in-memory macro operation, the set of multiple in-memory operations to be performed on data present in the memory media;

receive a single request to perform the in-memory macro operation;

determine, in response to the request, the set of multiple in-memory operations associated with the in-memory macro operation based on the single request; and

perform, in response to the single request, the set of multiple in-memory operations associated with the in-memory macro operation on data present in the memory media, wherein to perform further comprises to provide, to a component of a compute device in which the media access circuitry is located, status data indicating that the in-memory macro operation is in progress.