Image sensor with in-pixel background subtraction and motion detection

1. An imaging system, comprising:

an array of pixels configured to generate image charge voltage signals in response to incident light received from an external scene;

a control circuit coupled to the array of pixels to control operation of the array of pixels, wherein the control circuit is configured to control the array of pixels to capture a first image of the external scene and a second image of the external scene in sequence;

an infrared illumination source configured to illuminate the external scene in response to the control circuit, wherein the control circuit is configured to deactivate the infrared illumination source during the capture of the first image of the external scene, wherein the control circuit is configured to activate the infrared illumination source during the capture of the second image of the external scene;

an array of sample and hold circuits coupled to the array of pixels, wherein each one of the sample and hold circuits is coupled to a respective one of the pixels of the array of pixels, wherein each one of the sample and hold circuits comprises:

a first capacitor configured to store a first image charge voltage signal of the first image; and

a second capacitor configured to store a second image charge voltage signal of the second image; and

a column voltage domain differential amplifier coupled to the first capacitor and the second capacitor of each one of the sample and hold circuits in a column of the array of sample and hold circuits, wherein the column voltage domain differential amplifier is configured to determine a difference between the second image charge voltage signal and the first image charge voltage signal stored in each one of the sample and hold circuits to identify an object in a foreground of the external scene.

2. The imaging system of claim 1 , wherein the column voltage domain differential amplifier is further configured to detection motion in the external scene in response to the difference between the second image charge voltage signal and the first image charge voltage signal stored in each one of the sample and hold circuits.

3. The imaging system of claim 1 , wherein the infrared illumination source configured to generate infrared light having a wavelength substantially equal to 940 nanometers.

4. The imaging system of claim 3 , wherein the infrared illumination source configured to generate infrared light pulses having a pulse width substantially equal to 10 microseconds.

5. The imaging system of claim 4 , wherein the imaging system is configured to capture the first image of the external scene, capture the second image of the external scene, and determine the difference between the second image charge voltage signal and the first image charge voltage signal stored in each one of the sample and hold circuits 60 times per second.

6. The imaging system of claim 1 , wherein the first and second capacitors have capacitance values equal to approximately 130 femtofarads.

7. The imaging system of claim 1 , further comprising:

a first semiconductor die comprising the array of pixels; and

a second semiconductor die stacked with and coupled to the first semiconductor die, wherein the second semiconductor die comprises the array of sample and hold circuits and the readout circuit.

8. The imaging system of claim 7 , wherein each one of the pixels of the array of pixels comprises:

a photodiode configured to generate image charge in response to the incident light received from the external scene;

a floating diffusion configured to store the image charge generated by the photodiode;

a transfer gate coupled between the photodiode and the floating diffusion;

a reset transistor coupled between the floating diffusion and a supply voltage; and

a pixel source follower transistor having a gate coupled to the floating diffusion, a drain coupled to the supply voltage, and a source coupled to a hybrid bond at an interface between the first semiconductor die and the second semiconductor die.

9. The imaging system of claim 8 , wherein the drain of the pixel source follower transistor is coupled to the supply voltage through a first unswitched connection, wherein the source of the pixel source follower transistor is coupled to the hybrid bond through a second unswitched connection.

10. The imaging system of claim 8 , wherein each one of the sample and hold circuit further comprises:

a first sample and hold transistor coupled between the hybrid bond and the first capacitor;

a first source follower transistor having a gate coupled to the first capacitor;

a first row select transistor coupled between the first source follower transistor and a first input of the column voltage domain differential amplifier;

a second sample and hold transistor coupled between the hybrid bond and the second capacitor;

a second source follower transistor having a gate coupled to the second capacitor; and

a second row select transistor coupled between the first source follower transistor and a first input of the column voltage domain differential amplifier.

11. The imaging system of claim 10 , wherein each one of the sample and hold circuit further comprises a current source coupled between the hybrid bond and ground, wherein the current source comprises a current source transistor having a gate coupled to receive a bias voltage.

12. The imaging system of claim 11 , wherein each one of the sample and hold circuit further comprises a reference transistor coupled between the hybrid bond and a reference voltage, wherein the reference transistor is configured to provide the reference voltage to the hybrid bond in response to a reference voltage control signal.

13. The imaging system of claim 1 , wherein the column voltage domain differential amplifier is included in a readout circuit coupled to receive image charge voltage signals of the first image from the array of pixels and image charge voltage signals of the second image.