Slew-load characterization
Various implementations described herein are related to a method for constructing integrated circuitry and identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry. The method may include generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths. The method may include simulating corner points for the timing table, building diagonal points for the timing table based on the simulated corner points, and building remaining points for the timing table based on the simulated corner points and the diagonal points.
1. A method, comprising:
constructing integrated circuitry;
identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry, wherein the input signal paths refer to input clock signal paths and the internal signal paths refer to internal clock signal paths associated with logic within the integrated circuitry; and
generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths, including:
simulating corner points for the timing table;
building diagonal points for the timing table based on the simulated corner points; and
building remaining points for the timing table based on the simulated corner points and the diagonal points.
2. The method of claim 1 , wherein the integrated circuitry refers to chip-level circuitry for a system-on-a-chip (SoC), and wherein:
building the diagonal points for the timing table is achieved using geometric progression interpolation, and
building the remaining points for the timing table is achieved using a delta approach.
3. The method of claim 1 , wherein constructing integrated circuitry refers to generating a liberty model for the integrated circuitry having timing data and power data with multiple clock slews, multiple input slews and multiple output loads depending on a timing arc.
4. The method of claim 1 , wherein:
the input signal paths refer to the input clock signal paths and input data signal paths associated with the logic within the integrated circuitry,
the internal signal paths refer to the internal clock signal paths and internal data signal paths associated with the logic within the integrated circuitry, and
the output signal paths refer to delay signal paths associated with output from the integrated circuitry.
5. The method of claim 1 , wherein the slew-load characterization refers to timing, power and model data for slew/load variation for setup, hold, delay and pin-power arcs, and wherein the model data includes liberty variation format (LVF) model data and non-linear delay (NLD) model data for slew/load variation.
6. The method of claim 1 , wherein the timing table includes multiple points arranged in a two-dimensional (2D) grid pattern with columns and rows, and wherein the multiple points have point values associated with simulation values.
7. The method of claim 1 , wherein the timing table includes a scalable number (S) of points that are arranged with a first number (N) of columns and a second number (M) of rows, and wherein the scalable number of points includes (S=N*M) points that are arranged with N columns and M rows.
8. The method of claim 7 , wherein the scalable number (S) of points refers to forty-nine (49) points, wherein the first number (N) of columns refers to seven (7) columns, and wherein the second number (M) of rows refers to seven (7) rows.
9. The method of claim 8 , wherein:
the corner points for the timing table refer to a first corner point and a second corner point that is opposite the first corner point,
the diagonal points for the timing table refer to five (5) diagonal points along a central diagonal between the first corner point and the second corner point, and
the remaining points for the timing table refer to forty-two (42) remaining points that fill the timing table above and below the central diagonal.
10. An apparatus, comprising:
a processor; and
memory having instructions stored thereon that, when executed by the processor, cause the processor to:
construct integrated circuitry;
identify input signal paths, internal signal paths and output signal paths associated with the integrated circuitry, wherein the input signal paths refer to input clock signal paths and the internal signal paths refer to internal clock signal paths associated with logic within the integrated circuitry; and
generate a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths, including:
simulating corner points for the timing table;
building diagonal points for the timing table based on the simulated corner points, and
building remaining points for the timing table based on the simulated corner points and the diagonal points.
11. The apparatus of claim 10 , wherein:
building the diagonal points for the timing table is achieved using geometric progression interpolation, and
building the remaining points for the timing table is achieved using a delta approach.
12. The apparatus of claim 10 , wherein:
the input signal paths refer to the input clock signal paths and input data signal paths associated with the logic within the integrated circuitry,
the internal signal paths refer to the internal clock signal paths and internal data signal paths associated with the logic within the integrated circuitry, and
the output signal paths refer to delay signal paths associated with output from the integrated circuitry.
13. The apparatus of claim 10 , wherein:
constructing integrated circuitry refers to generating a liberty model for the integrated circuitry having timing data and power data with multiple clock slews, multiple input slews and multiple output loads depending on a timing arc, and
the slew-load characterization refers to timing, power and model data for slew/load variation for setup, hold, delay and pin-power arcs, and wherein the model data includes liberty variation format (LVF) model data and non-linear delay (NLD) model data for slew/load variation.
14. The apparatus of claim 10 , wherein the timing table includes multiple points arranged in a two-dimensional (2D) grid pattern with columns and rows, and wherein the multiple points have point values associated with simulation values.
15. The apparatus of claim 10 , wherein the timing table includes a scalable number (S) of points that are arranged with a first number (N) of columns and a second number (M) of rows, and wherein the scalable number of points includes (S=N*M) points that are arranged with N columns and M rows.
16. The apparatus of claim 15 , wherein the scalable number (S) of points refers to forty-nine (49) points, wherein the first number (N) of columns refers to seven (7) columns, and wherein the second number (M) of rows refer to seven (7) rows.
17. The apparatus of claim 16 , wherein:
the corner points for the timing table refer to a first corner point and a second corner point that is opposite the first corner point,
the diagonal points for the timing table refer to five (5) diagonal points along a central diagonal between the first corner point and the second corner point, and
the remaining points for the timing table refer to forty-two (42) remaining points that fill the timing table above and below the central diagonal.
18. A non-transitory computer-readable medium having computer-executable instructions stored thereon that, when executed by a computer, cause the computer to:
construct integrated circuitry;
identify input signal paths, internal signal paths and output signal paths associated with the integrated circuitry, wherein the input signal paths refer to input clock signal paths and the internal signal paths refer to internal clock signal paths associated with logic within the integrated circuitry; and
generate a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths, including:
simulating corner points for the timing table;
building diagonal points for the timing table based on the simulated corner points; and
building remaining points for the timing table based on the simulated corner points and the diagonal points.
19. The computer-readable medium of claim 18 , wherein:
building the diagonal points for the timing table is achieved using geometric progression interpolation,
building the remaining points for the timing table is achieved using a delta approach,
the input signal paths refer to the input clock signal paths and input data signal paths associated with the logic within the integrated circuitry,
the internal signal paths refer to the internal clock signal paths and internal data signal paths associated with the logic within the integrated circuitry, and
the output signal paths refer to delay signal paths associated with output from the integrated circuitry.
20. The computer-readable medium of claim 18 , wherein:
the timing table includes multiple points arranged in a two-dimensional (2D) grid pattern with columns and rows,
the multiple points have point values associated with simulation values,
the timing table includes a scalable number (S) of points that are arranged with a first number (N) of columns and a second number (M) of rows, and
the scalable number of points includes (S=N*M) points that are arranged with N columns and M rows.