IP Library Granted Patent US 11,624,985
Granted Patent B2
US 11,624,985 · App. 17/063,386 · Granted Apr 11, 2023

Methods of defect inspection

Inventors: Ta-Ching Yu (Zhubei, TW); Shih-Che Wang (Hsinchu, TW); Shu-Hao Chang (Taipei, TW); Yi-Hao Chen (New Taipei, TW); Chen-Yen Kao (Hsinchu, TW); Te-Chih Huang (Hsinchu, TW); Yuan-Fu Hsu (Taichung, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
G03F7/7065G01N21/8901G01N21/956G06T7/0006H01L21/0275H01L22/24H01L22/30G01N2021/8825G06T2207/10061H01L22/12
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Quick Facts
Patent No.
US 11,624,985
App. No.
17/063,386
Granted
Apr 11, 2023
Kind
B2
Abstract

Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.

Claims (38)

1. A method of inspecting defects, comprising:

forming openings in an underlying layer by etching using a patterned photoresist layer as an etching mask, the openings formed by etching including at least one defective pattern;

forming a filling material layer in the openings and over an upper surface of the underlying layer;

performing a planarization operation such that the upper surface of the underlying layer is exposed and the filling material layer remains in the opening; and

after the planarization operation and with the filling material layer in the openings, performing an inspection operation to find a defective pattern corresponding to the at least one defective pattern in the underlying layer using an optical inspection tool, wherein:

the at least one defective pattern includes one of a defect in size or a connection of patterns, and

the filling material comprises an organic material or a dielectric material.

2. The method of claim 1 , wherein the planarization operation includes a chemical mechanical polishing (CMP) operation.

3. The method of claim 2 , wherein the filling material comprises an organic bottom anti-reflective coating (BARC) material.

4. The method of claim 1 , wherein the filling material comprises a photo resist containing dye.

5. The method of claim 2 , wherein the underlying layer comprises at least one of amorphous silicon, aluminum oxide or hafnium oxide.

6. The method of claim 1 , wherein the filling material comprises at least one of aluminum oxide or hafnium oxide.

7. The method of claim 6 , wherein the underlying layer includes a conductive material layer.

8. The method of claim 6 , wherein the filling material is formed by one of an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process.

9. A method of manufacturing a semiconductor device, comprising:

forming a first layer over a substrate;

forming a second layer over the first layer;

patterning the second layer and the first layer to form openings by using a patterned photoresist layer as an etching mask, the openings pass through the second layer;

forming a filling material layer in the openings and over an upper surface of the second layer;

performing a planarization operation such that the upper surface of the second layer is exposed and the filling material layer remains in the opening; and

with the filling material layer in the openings, performing an inspection operation to find a defective pattern in the second layer using an optical inspection tool,

wherein the filling material comprises at least one of amorphous silicon, or hafnium oxide.

10. The method of claim 9 , wherein the performing the inspection operation comprises selecting an inspection wavelength or inspection spectrum by comparing attenuation coefficients, relative permittivities, or reflection coefficients between the filling material and the second layer.

11. The method of claim 9 , wherein the openings do not pass through the first layer.

12. The method of claim 9 , wherein a reflection of the filling material with respect to an inspection light of the optical inspection tool is higher than a reflection of the second layer with respect to the inspection light.

13. The method of claim 9 , wherein a reflection of the filling material with respect to an inspection light of the optical inspection tool is lower than a reflection of the second layer with respect to the inspection light.

14. The method of claim 9 , wherein the second layer includes a metallic material layer.

15. The method of claim 14 , wherein the filling material comprises hafnium oxide.

16. The method of claim 15 , wherein the filling material is formed by one of an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or a physical vapor deposition (PVD) process.

17. A method for semiconductor processing, comprising:

forming pattern features in an underlying layer;

filling the pattern features with a dummy filling material made of an organic material by disposing the dummy filling material in the pattern features and over the underlying layer and performing an etching operation to remove an excess portion of the dummy filling material to expose the underlying layer;

selecting an inspection wavelength or inspection spectrum by comparing attenuation coefficients, relative permittivities, or reflection coefficients between the underlying layer and the dummy filling material;

after the pattern features are filled with the dummy filling material, inspecting filled pattern features for defects by using the selected inspection wavelength or inspection spectrum; and

after the inspecting, removing the dummy filling material by using a plasma ashing process.

18. The method of claim 17 , wherein the underlying layer is made of silicon oxide.

19. The method of claim 18 , wherein the inspection spectrum is between 250 nm and 255 nm.

20. The method of claim 17 , wherein a critical dimension of the pattern features inspected is less than 30 nanometers.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2020
From: YU, TA-CHING; WANG, SHIH-CHE; CHANG, SHU-HAO; KAO, CHEN-YEN; HUANG, TE-CHIH; HSU, YUAN-FU
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 053976/0728 →
Continuity (3)
Continuation 15833640 · Dec 6, 2017
Provisional Application 62550113 · Aug 25, 2017
Related Publication 20210018848A1 · Jan 21, 2021