Wear leveling in EEPROM emulator formed of flash memory cells
The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. The embodiments comprise a system and method for receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and when the current word is not the last physical word in the sector, changing a next index bit.
1. A EEPROM emulated system with wear leveling, comprising:
an EEPROM emulated array comprising an array of non-volatile memory cells; and
a wear leveling module coupled to the array of non-volatile memory cells and configured to:
receive an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in the array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word;
when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and
when the current word is not the last physical word in the sector, changing a next index bit.
2. The system of claim 1 , wherein the index bit is a bit in an index word.
3. The system of claim 2 , wherein the index word comprises a set of bits, wherein each bit in the index word corresponds to a physical word in the array.
4. The system of claim 3 , wherein each bit in the index word indicates whether a corresponding physical word in the array is used or not used.
5. The system of claim 4 , wherein the step of changing a next bit in the index word comprises programming a “0” in the index word for a bit position corresponding to the next word.
6. The system of claim 1 , wherein the sector comprises two rows of non-volatile memory cells in the array of non-volatile memory cells.
7. The system of claim 1 , wherein each of the non-volatile memory cells comprises a bit line terminal, a source line terminal, a word line terminal, and a floating gate.
8. The system of claim 7 , wherein each of the non-volatile memory cells further comprises a control gate.
9. The system of claim 8 , wherein each of the non-volatile memory cells further comprises an erase gate.
10. A method of performing wear leveling in an EEPROM emulated system, the method comprising:
receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word;
when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and
when the current word is not the last physical word in the sector, changing a next index bit.
11. The method of claim 10 , wherein the index bit is a bit in an index word.
12. The method of claim 11 , wherein the index word comprises a set of bits, wherein each bit in the index word corresponds to a physical word in the array.
13. The method of claim 12 , wherein each bit in the index word indicates whether a corresponding physical word in the array is used or not used.
14. The method of claim 13 , wherein the step of changing a next bit in the index word comprises programming a “0” in the index word for a bit position corresponding to the next word.
15. The method of claim 10 , wherein the sector comprises two rows of non-volatile memory cells in the array of non-volatile memory cells.
16. The method of claim 10 , wherein each of the non-volatile memory cells comprises a bit line terminal, a source line terminal, a word line terminal, and a floating gate.
17. The method of claim 16 , wherein each of the non-volatile memory cells further comprises a control gate.
18. The method of claim 17 , wherein each of the non-volatile memory cells further comprises an erase gate.