Semiconductor packages including antenna pattern
A semiconductor package having a thinner shape and including an antenna is provided. A semiconductor package comprises a first substrate, a second substrate on the first substrate and including a first face facing the first substrate and a second face opposite to the first face, a pillar extending from the second face of the second substrate to the first substrate, and a first semiconductor chip on the second face of the second substrate and connected to the pillar. The second substrate may include an antenna pattern, and the antenna pattern may be connected to the first semiconductor chip, and may be on the second face of the second substrate such that the antenna pattern is isolated from direct contact with the first semiconductor chip.
1. A semiconductor package, comprising:
a first substrate;
a second substrate on the first substrate, the second substrate including a first face facing the first substrate and a second face opposite to the first face;
a pillar extending from the second face of the second substrate to the first substrate; and
a first semiconductor chip on the second face of the second substrate and connected to the pillar,
wherein the second substrate includes an antenna pattern,
wherein the antenna pattern is connected to the first semiconductor chip, and the antenna pattern is on the second face of the second substrate such that the antenna pattern is isolated from direct contact with the first semiconductor chip,
wherein the second substrate is between the antenna pattern and the first substrate, and the second substrate is between the first semiconductor chip and the first substrate.
2. The semiconductor package of claim 1 , wherein the first semiconductor chip includes an RFIC (radio frequency integrated circuit) chip.
3. The semiconductor package of claim 1 , wherein
the first substrate includes
a third face facing the second substrate, and
a fourth face opposite to the third face, and
the pillar is connected to the third face of the first substrate.
4. The semiconductor package of claim 3 , wherein
the first substrate includes a wiring structure,
a part of the wiring structure is exposed on the third face of the first substrate, and
the wiring structure is connected to the pillar.
5. The semiconductor package of claim 1 , further comprising:
a molded layer which is between the first substrate and the second substrate,
wherein the pillar penetrates the molded layer.
6. The semiconductor package of claim 5 , wherein a length of the pillar is equal to or greater than a thickness of the molded layer.
7. The semiconductor package of claim 1 , further comprising:
a second semiconductor chip,
wherein the second semiconductor chip is between the first substrate and the second substrate, and the second semiconductor chip is connected to the first substrate.
8. The semiconductor package of claim 7 , wherein the second semiconductor chip is connected to the first semiconductor chip through the pillar and the first substrate.
9. The semiconductor package of claim 1 , wherein
the second substrate includes a wiring and a ground pattern,
the wiring and the ground pattern are at least partially within an interior of the second substrate, and
the antenna pattern and the first semiconductor chip are connected by the wiring.
10. The semiconductor package of claim 9 , wherein an upper face of the wiring is exposed on the second face of the second substrate.
11. The semiconductor package of claim 1 , further comprising:
an electromagnetic wave shielding film which extends along an upper face and side walls of the first semiconductor chip.
12. The semiconductor package of claim 11 , further comprising:
a heat slug which extends along an upper face of the electromagnetic wave shielding film.
13. The semiconductor package of claim 1 , further comprising:
a first molded layer between the first substrate and the second substrate; and
a second molded layer between the first molded layer and the first semiconductor chip,
wherein the first semiconductor chip is on the second molded layer,
wherein the pillar penetrates the first and second molded layers and extends to the first substrate.
14. A semiconductor package, comprising:
a first substrate;
a second substrate on the first substrate, the second substrate including a first face facing the first substrate and a second face opposite to the first face;
a first pillar and a second pillar extending from the second face of the second substrate to the first substrate; and
a semiconductor chip on the second face of the second substrate, the semiconductor chip including a first signal terminal, a second signal terminal, and a power terminal,
wherein the second substrate includes an antenna pattern connected to the first signal terminal of the semiconductor chip,
wherein the first pillar is connected to the power terminal, and the second pillar is connected to the second signal terminal.
15. The semiconductor package of claim 14 , wherein the antenna pattern is at least partially on a side wall of the second substrate.
16. The semiconductor package of claim 14 , wherein the semiconductor chip connects the first signal terminal and the second signal terminal.
17. The semiconductor package of claim 14 , further comprising:
an electromagnetic wave shielding film which extends along an upper face and side walls of the semiconductor chip.
18. The semiconductor package of claim 14 , wherein a distance between the first signal terminal of the semiconductor chip and the antenna pattern is smaller than a length of at least one of the first pillar or the second pillar.
19. The semiconductor package of claim 14 , wherein a thickness of the second substrate is smaller than a thickness of the first substrate.
20. A semiconductor package, comprising:
a first substrate including a first face and a second face opposite to each other;
a plurality of connection terminals on the first face of the first substrate;
a first semiconductor chip and a passive element on the second face of the first substrate;
a molded layer which covers the first semiconductor chip and the passive element, the molded layer being on the second face of the first substrate;
a second substrate on the molded layer, the second substrate including a third face facing the molded layer and a fourth face opposite to the third face;
a plurality of pillars extending from the fourth face of the second substrate to the second face of the first substrate to penetrate the second substrate and the molded layer; and
a second semiconductor chip on the fourth face of the second substrate and connected to the plurality of pillars,
wherein a first pillar of the plurality of pillars is connected to the first semiconductor chip and the passive element through the first substrate,
wherein a second pillar of the plurality of pillars is connected to one connection terminal of the plurality of connection terminals through the first substrate,
wherein the second substrate includes an antenna pattern, a ground pattern, and wiring,
wherein the antenna pattern is connected to the second semiconductor chip through the wiring, and the antenna pattern is on the fourth face of the second substrate to be isolated from direct contact with the second semiconductor chip, and
wherein the ground pattern is in the second substrate.