IP Library › Granted Patent US 11,626,394
Granted Patent B2
US 11,626,394 · App. 17/184,837 · Granted Apr 11, 2023

Semiconductor storage device

Inventors: Akihiko Chiba (Yokohama Kanagawa, JP); Takahiro Tsurudo (Yokohama Kanagawa, JP); Kenichi Matoba (Yokohama Kanagawa, JP); Yoshifumi Shimamura (Yokohama Kanagawa, JP); Hiroaki Nakasa (Yokohama Kanagawa, JP); Hiroyuki Takenaka (Kamakura Kanagawa, JP)
Assignee: KIOXIA CORPORATION
H01L25/18H01L23/5286H01L24/08H01L2224/08145H01L2924/14511
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Quick Facts
Patent No.
US 11,626,394
App. No.
17/184,837
Granted
Apr 11, 2023
Kind
B2
Abstract

A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.

Claims (15)

1. A semiconductor storage device, comprising:

a first semiconductor chip having a first bonding surface extending along a first direction and a second direction orthogonal to the first direction; and

a second semiconductor chip having a second bonding surface extending along the first direction and the second direction, the second bonding surface being bonded to the first bonding surface, wherein

the first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in the first direction, and a first pad electrode disposed on the first bonding surface,

the second semiconductor chip includes a second power line extending in the second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface, and

the first power line and the second power line are bonded to each other through the first pad electrode and the third pad electrode, and the first power line is coupled to the second pad electrode via the third power line.

2. The semiconductor storage device according to claim 1 , wherein

the first power line, connected to the control circuit and extending in the first direction, connected to the second power line above the control circuit in a third direction orthogonal to the first direction and the second direction.

3. The semiconductor storage device according to claim 1 , wherein

a terminal portion of the second power line is connected to the second pad electrode.

4. The semiconductor storage device according to claim 1 , wherein

the second pad electrode is disposed on a surface opposite to the second bonding surface.

5. The semiconductor storage device according to claim 1 , wherein the first power line is configured to conduct a first current capacity, the second power line is configured to conduct a second current capacity, and the third power line is configured to conduct a third current capacity.

6. The semiconductor storage device according to claim 5 , wherein the third current capacity is greater than the second current capacity, and the second current capacity is greater than the first current capacity.

7. The semiconductor storage device according to claim 1 , wherein the second semiconductor chip includes a three dimensional memory cell array.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2021
From: CHIBA, AKIHIKO; TSURUDO, TAKAHIRO; MATOBA, KENICHI; SHIMAMURA, YOSHIFUMI; NAKASA, HIROAKI; TAKENAKA, HIROYUKI
To: KIOXIA CORPORATION
Reel/Frame 056357/0631 →
Priority Claims (1)
JP JP2020-149193 · Sep 4, 2020 · national
Continuity (1)
Related Publication 20220077128A1 · Mar 10, 2022