Low-leakage regrown GaN p-n junctions for GaN power devices
Fabricating a regrown GaN p-n junction includes depositing a n-GaN layer on a substrate including n + -GaN, etching a surface of the n-GaN layer to yield an etched surface, depositing a p-GaN layer on the etched surface, etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate, and passivating a portion of the p-GaN layer around an edge of the mesa. The regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer. The regrown GaN p-n junction includes a substrate, a n-GaN layer on the substrate having an etched surface, a p-GaN layer on the etched surface, a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer, and a passivated portion of the p-GaN layer around an edge of the mesa.
1. A method for fabricating a regrown GaN p-n junction, the method comprising:
depositing a n-GaN layer on a substrate comprising n + -GaN;
etching a surface of the n-GaN layer to yield an etched surface;
depositing a p-GaN layer on the etched surface;
etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate; and
passivating a portion of the p-GaN layer around an edge of the mesa,
wherein the regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer.
2. The method of claim 1 , wherein the n-GaN layer is unintentionally doped.
3. The method of claim 1 , wherein depositing the n-GaN layer comprises metalorganic chemical vapor deposition.
4. The method of claim 1 , wherein etching the surface of the n-GaN layer comprises wet etching.
5. The method of claim 1 , wherein etching the surface of the n-GaN layer occurs in multiple steps.
6. The method of claim 5 , wherein the multiple steps decrease in power.
7. The method of claim 5 , wherein etching the surface of the n-GaN layer occurs in four steps of decreasing power.
8. The method of claim 1 , further comprising cleaning the etched surface before depositing the p-GaN layer.
9. The method of claim 1 , further comprising depositing an insertion layer between the etched surface and the p-GaN layer.
10. The method of claim 1 , further comprising activating the p-GaN layer before etching the portion of the n-GaN layer and the portion of the p-GaN layer.
11. The method of claim 1 , wherein etching the portion of the n-GaN layer and the portion of the p-GaN layer comprises dry etching.
12. The method of claim 1 , wherein passivating the portion of the p-GaN layer comprises hydrogen-plasma passivation.
13. The method of claim 1 , further comprising depositing a first metal stack on an outer surface of the p-GaN layer and a second metal stack on an outer surface of the substrate.
14. The method of claim 13 , further comprising subjecting the first metal stack and the second metal stack to rapid thermal annealing.
15. A regrown GaN p-n junction comprising:
a substrate;
a n-GaN layer on the substrate, wherein a surface of the n-GaN layer is etched;
a p-GaN layer on the etched surface;
a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer; and
a passivated portion of the p-GaN layer around an edge of the mesa,
wherein an interface between the n-GaN layer and the p-GaN layer defines the regrown GaN p-n junction.
16. The regrown GaN p-n junction of claim 15 , wherein the substrate comprises n + -GaN.
17. The regrown GaN p-n junction of claim 15 , further comprising an insertion layer between the n-GaN layer and the p-GaN layer.
18. The regrown GaN p-n junction of claim 15 , wherein a differential on- resistance of the GaN p-n junction is about 8 mΩ cm 2 .
19. A device comprising the regrown GaN p-n junction of claim 15 .
20. The device of claim 19 , wherein the device comprises a junction barrier Schottky diode, a device with floating field rings, a field effect transistor, or a bipolar junction transistor.