Interconnect structure to reduce contact resistance, electronic device including the same, and method of manufacturing the interconnect structure
An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.
1. An interconnect structure comprising:
a semiconductor layer including a first region having a doping concentration higher than a doping concentration of a peripheral region of the semiconductor layer;
a metal layer facing the semiconductor layer;
a graphene layer between the semiconductor layer and the metal layer; and
a conductive metal oxide layer between the graphene layer and the semiconductor layer and covering the first region.
2. The interconnect structure of claim 1 , further including
an insulating layer on the semiconductor layer, the insulating layer including a via hole through which the first region is exposed, wherein
the conductive metal oxide layer, the graphene layer, and the metal layer are sequentially stacked in the via hole.
3. The interconnect structure of claim 1 , further comprising:
a metal silicide layer between the semiconductor layer and the conductive metal oxide layer.
4. The interconnect structure of claim 1 , further comprising:
a metal carbide layer between the graphene layer and the conductive metal oxide layer.
5. The interconnect structure of claim 3 , further comprising:
a metal carbide layer between the graphene layer and the conductive metal oxide layer.
6. The interconnect structure of claim 1 , wherein the conductive metal oxide layer includes a two-component conductive metal oxide layer, a three-component conductive metal oxide layer, or a four-component conductive metal oxide layer.
7. The interconnect structure of claim 1 , wherein the graphene layer includes nanocrystalline graphene (nc-G) or a graphene sheet.
8. An electronic device comprising:
a transistor; and
a data storage element connected to the transistor,
wherein the transistor and the data storage element are connected to each other through the interconnect structure of claim 1 .
9. The electronic device of claim 8 , wherein the data storage element includes a ferroelectric capacitor including:
a lower electrode in contact with the interconnect structure;
a dielectric layer on the lower electrode; and
an upper electrode on the dielectric layer.
10. The electronic device of claim 8 , further comprising:
a metal silicide layer between the conductive metal oxide layer and the semiconductor layer in the interconnect structure.
11. The electronic device of claim 8 , further comprising:
a metal carbide layer between the graphene layer and the conductive metal oxide layer in the interconnect structure.
12. The electronic device of claim 8 , wherein the graphene layer includes nc-G or a graphene sheet.
13. The electronic device of claim 8 , wherein the conductive metal oxide layer includes a two-component conductive metal oxide layer, a three-component conductive metal oxide layer, or a four-component conductive metal oxide layer.
14. An electronic device comprising:
a first semiconductor layer having a first doped region;
a multi-quantum well layer on the first semiconductor layer so as not to contact the first doped region;
a second semiconductor layer on the multi-quantum well layer and having a second doped region;
a first connect layer and a first metal layer sequentially stacked on the first doped region; and
a second connect layer and a second metal layer sequentially stacked on the second doped region, wherein
each of the first and second connect layers includes a conductive metal oxide layer and a graphene layer on the conductive metal oxide layer.
15. The electronic device of claim 14 , further comprising:
a metal silicide layer between the conductive metal oxide layer and the first and second doped regions.
16. The electronic device of claim 14 , further comprising:
a metal carbide layer between the graphene layer and the conductive metal oxide layer.
17. The electronic device of claim 14 , wherein the graphene layer includes nc-G or a graphene sheet.
18. The electronic device of claim 14 , wherein the conductive metal oxide layer includes a two-component conductive metal oxide layer, a three-component conductive metal oxide layer, or a four-component system conductive metal oxide layer.
19. A method of manufacturing an interconnect structure, the method comprising:
forming a first doped region in a semiconductor layer, the first doped region having a doping concentration greater than a doping concentration of a peripheral region in the semiconductor layer;
sequentially stacking a conductive metal oxide layer, a graphene layer, and a metal layer covering the first doped region on the semiconductor layer;
forming a mask on the metal layer to cover a portion of the first doped region;
sequentially etching the metal layer, the graphene layer, and the conductive metal oxide layer around the mask; and
removing the mask.
20. The method of claim 19 , further comprising:
forming a metal silicide layer between the conductive metal oxide layer and the semiconductor layer, wherein
the sequentially etching further comprises etching the metal silicide layer around the mask.
21. The method of claim 19 , further comprising:
forming a metal carbide layer between the conductive metal oxide layer and the graphene layer, wherein
the sequentially etching further comprises etching the metal carbide layer around the mask.
22. A method of manufacturing an interconnect structure, the method comprising:
forming a first doped region in a semiconductor layer, the first doped region having a doping concentration greater than a doping concentration of a peripheral region in the semiconductor layer;
forming a mask exposing a portion of the first doped region on the semiconductor layer to provide an exposed area of the first doped region;
sequentially stacking a conductive metal oxide layer, a graphene layer, and a metal layer covering the exposed area of the first doped region; and
removing the mask.
23. The method of claim 22 , further comprising:
forming a metal silicide layer between the conductive metal oxide layer and the semiconductor layer.
24. The method of claim 22 , further comprising:
forming a metal carbide layer between the conductive metal oxide layer and the graphene layer.