Dual compare ternary content addressable memory
A ternary content addressable memory (TCAM) semiconductor device includes a first and second data storage portions each connected to a bit line. The first data storage portion is connected to a first word line, and to a first and third group of in series transistors. The second data storage portion is connected to a second word line, and to a second and fourth group of in series transistors. The first group and second group of in series transistors are each connected to a first match line. The first group is connected to a first search line bar, and the second group is connected to a first search line. A third and fourth group of in series transistors are each connected to a second match line. The third group is connected to a second search line, and the fourth group is connected to a second search line bar.
1. A semiconductor device comprising:
a first data storage portion;
a second data storage portion;
the first and second data storage portions each connected to a bit line;
the first data storage portion connected to a first word line;
the second data storage portion connected to a second word line;
a first group of in series transistors connected to a first match line;
a second group of in series transistors connected to the first match line;
the first group of in series transistors connected to a first search line bar; and
the second group of in series transistors connected to a first search line;
a third group of in series transistors connected to a second match line;
a fourth group of in series transistors connected to the second match line;
the third group of in series transistors connected to a second search line;
the fourth group of in series transistors connected to a second search line bar;
the first data storage portion connected to the first group and third group of in series transistors; and
the second data storage portion connected to the second group and fourth group of in series transistors.
2. The semiconductor device of claim 1 , wherein each of the first and second data storage portions comprise an electronic circuit including a first and second cross-coupled inverter, and a first and second transistor, wherein an output of the first cross-coupled inverter is connected to the first transistor and is connected to an input of the second cross-coupled inverter, and an output of the second cross-coupled inverter is connected to the second transistor and is connected to an input of the first cross-coupled inverter.
3. The semiconductor device of claim 1 , wherein the first data storage portion and the second data storage portion are each connected to a bit line bar.
4. The semiconductor device of claim 1 , wherein each of the group of in series transistors is connected to ground.
5. The semiconductor device of claim 1 , wherein the first group of in series transistors is connected to the second group of in series transistors; and
the third group of in series transistors is connected to the fourth group of in series transistors.
6. The semiconductor device of claim 1 , further comprising:
a third data storage portion;
a fourth data storage portion;
the third and fourth data storage portions each connected to a second bit line;
the third data storage portion connected to the first word line; and
the fourth data storage portion connected to a second word line.
7. The semiconductor device of claim 6 , wherein each of the third and fourth data storage portions comprise an electronic circuit including a third and fourth cross-coupled inverter, and a third and fourth transistor, wherein an output of the third cross-coupled inverter is connected to the third transistor and is connected to an input of the fourth cross-coupled inverter, and an output of the fourth cross-coupled inverter is connected to the fourth transistor and is connected to an input of the third cross-coupled inverter.
8. The semiconductor device of claim 6 , wherein the third data storage portion and the fourth data storage portion are each connected to a second bit line bar.
9. A method of operating a ternary content addressable memory device (TCAM), the method comprising:
receiving, by the TCAM, a first search criteria, the TCAM including a first and second storage portion, a first and second compare port, a first and second search line, a first and second search line bar, a first and second match line, and a first and second word line;
receiving, by the TCAM, a second search criteria;
performing, by the TCAM, a first search of the first and second storage portion using the first compare port with the first search criteria;
performing, by the TCAM, a second search of the first and second storage portion using the second compare port with the second search criteria;
determining, by the TCAM, a first search output for the first search criteria; and
determining, by the TCAM, a second search output for the second search criteria.
10. The method of claim 9 , comprising:
prior to performing the first and second search by the TCAM, charging the first and second match lines to a high voltage.
11. The method of claim 9 , comprising:
prior to performing the first and second search by the TCAM, charging the first and second search lines to ground.
12. The method of claim 10 , comprising:
determining, by the TCAM, whether the first match line has been pulled down to a lower voltage than the charged high voltage; and
determining, by the TCAM, whether the second match line has been pulled down to a lower voltage than the charged high voltage.
13. The method of claim 9 , wherein the first search and second search are performed concurrently during a single computer processing unit (CPU) clock cycle.