Method of fabricating self-aligned via structures
Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
1. A method, comprising:
forming a layer stack over a substrate, the layer stack comprising:
a first glue layer over the substrate,
a first metal layer over the first glue layer,
an etch stop layer over the first metal layer,
a second metal layer over the etch stop layer,
a second glue layer over the second metal layer,
a cap layer over the second metal layer;
etching the layer stack to form a first opening and a second opening through the layer stack to expose a first portion of the substrate and define a stack feature formed from the layer stack;
depositing a protection layer over a top surface of the stack feature, sidewalls of the stack feature and the first portion of the substrate;
depositing a mask layer over the protection layer;
patterning the mask layer to form a third opening to expose the protection layer disposed on one of the sidewalls of the stack feature;
depositing a reverse material in the third opening;
after the depositing the reverse material, removing the mask layer;
performing an anisotropic etch to remove the protection layer, the cap layer, the second glue layer, and the second metal layer of the stack feature to form a conductive line feature;
removing the reverse material; and
depositing an interlayer dielectric (ILD) layer over the conductive line feature.
2. The method of claim 1 ,
wherein a composition of the first glue layer is different from a composition of the first metal layer, and
wherein a composition of the second glue layer is different from a composition of the second metal layer.
3. The method of claim 1 , wherein the etch stop layer is electrically conductive.
4. The method of claim 3 ,
wherein a composition of the etch stop layer is different from a composition of the first metal layer, and
wherein the composition of the etch stop layer is different from a composition of the second metal layer.
5. The method of claim 1 , further comprising:
before the depositing of the ILD layer, depositing a barrier layer over the substrate and the conductive line feature.
6. The method of claim 5 , further comprising:
after the depositing the barrier layer, annealing the barrier layer to enhance adhesion between the barrier layer and the first metal layer.
7. The method of claim 6 , wherein the annealing comprises an anneal temperature between about 200° C. and about 500° C.
8. The method of claim 1 , wherein the protection layer comprises silicon, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, metal nitride, metal oxide, or a combination thereof.
9. A method, comprising:
forming a layer stack over a substrate, the layer stack comprising:
a first metal layer over the substrate,
an etch stop layer over the first metal layer,
a second metal layer over the etch stop layer, and
a cap layer over the second metal layer;
etching the layer stack to form a first opening and a second opening through the layer stack to expose a portion of the substrate and define a stack feature formed from the layer stack;
depositing a protection layer over a top surface of the stack feature, sidewalls of the stack feature and the portion of the substrate;
depositing a mask layer over the protection layer;
patterning the mask layer to form a third opening to expose the protection layer disposed on a portion of the top surface of the stack feature;
depositing a reverse material in the third opening;
after the depositing the reverse material, removing the mask layer;
performing an anisotropic etch to trim the cap layer and the second metal layer to form a conductive line feature out of the second metal layer of the stack feature and a via feature over the conductive line feature out of the first metal layer of the stack feature;
removing the reverse material and the protection layer over the conductive line feature and the via feature; and
depositing an interlayer dielectric (ILD) layer over the via feature and the conductive line feature.
10. The method of claim 9 , wherein a width of the via feature is smaller than a width of the conductive line feature.
11. The method of claim 9 , wherein the ILD layer is deposited on a portion of the top surface of the etch stop layer on the first metal layer.
12. The method of claim 9 , wherein the layer stack further comprises:
a first glue layer sandwiched between the substrate and the first metal layer; and
a second glue layer sandwiched between the second metal layer and the cap layer.
13. The method of claim 12 ,
wherein a composition of the first glue layer is different from a composition of the first metal layer, and
wherein a composition of the second glue layer is different from a composition of the second metal layer.
14. The method of claim 9 , wherein the etch stop layer is electrically conductive.
15. The method of claim 9 ,
wherein a composition of the etch stop layer is different from a composition of the first metal layer, and
wherein the composition of the etch stop layer is different from a composition of the second metal layer.
16. The method of claim 9 , further comprising:
before the depositing of the ILD layer, depositing a barrier layer over the substrate and the conductive line feature.
17. An interconnect structure, comprising:
a substrate;
a conductive line over the substrate, the conductive line comprising:
a glue layer,
a metal layer disposed directly on the glue layer, and
a conductive etch stop layer disposed directly on the metal layer;
a barrier layer disposed on a top surface and sidewalls of the conductive line; and
an interlayer dielectric (ILD) layer over the barrier layer.
18. The interconnect structure of claim 17 , wherein a composition of the conductive etch stop layer is different from a composition of the metal layer.
19. The interconnect structure of claim 17 , wherein the barrier layer is disposed directly on sidewalls of the glue layer and the conductive etch stop layer.
20. The interconnect structure of claim 17 , wherein a composition of the glue layer is different from a composition of the metal layer.