IP Library › Granted Patent US 11,631,687
Granted Patent B2
US 11,631,687 · App. 16/797,331 · Granted Apr 18, 2023

Vertical memory device with improved manufacturing yield

Inventors: Yusaku Suzuki (Kuwana, JP); Kazuhiro Nojima (Mie, JP); Atsuko Aiba (Kuwana, JP)
Assignee: Kioxia Corporation
H01L27/1157G11C16/0483H01L27/11565
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Quick Facts
Patent No.
US 11,631,687
App. No.
16/797,331
Granted
Apr 18, 2023
Kind
B2
Abstract

A semiconductor memory device according to an embodiment includes a base, a first conductor, a second conductor, a first pillar, a first insulating member, and a first contact. The first conductor is provided in a first layer above the base. The second conductor is provided above the first conductor. The first pillar includes a first portion and a second portion formed by different bodies. The first portion of the first pillar is provided to penetrate the first conductor. The second portion of the first pillar is provided to penetrate the second conductor. The first insulating member is provided at least in the first layer. The first contact is contacting the second conductor above the first insulating member.

Claims (85)

1. A semiconductor memory device comprising:

a base;

a first conductor provided in a first layer above the base;

a second conductor provided above the first conductor;

a first pillar including a first portion and a second portion formed by different bodies, the first portion of the first pillar being provided to penetrate the first conductor, and the second portion of the first pillar being provided to penetrate the second conductor;

a first insulating member provided at least in the first layer; and

a first contact contacting the second conductor above the first insulating member and overlapping the first insulating member in a direction perpendicular to a surface of the base, wherein

in the first layer, the first conductor does not overlap the first insulating member in the direction perpendicular to the surface of the base.

2. The device of claim 1 , further comprising:

a third conductor provided above the second conductor, each of the second portion of the first pillar and the first contact penetrating the third conductor, wherein

an intersection portion between the first conductor and the first pillar functions as a memory cell transistor, and

an intersection portion between the second and third conductors and the first pillar functions as a select transistor.

3. The device of claim 1 , further comprising:

a fourth conductor provided in a second layer between the base and the first conductor, the first portion of the first pillar penetrating the fourth conductor; and

a second insulating member provided in the second layer and between the base and the first insulating member, wherein

the first insulating member and the second insulating member include an identical material.

4. The device of claim 3 , further comprising:

a first insulating layer provided between the first conductor and the fourth conductor; and

a second insulating layer provided between the first insulating member and the second insulating member, wherein

the first insulating layer and the second insulating layer include an identical insulating material.

5. The device of claim 3 , wherein

a plurality of second conductors are provided to extend in a first direction, the second conductors being arranged in a second direction crossing the first direction, and

a plurality of first contacts are provided in contact with the second conductors, respectively, the first contacts overlapping the first insulating member and the second insulating member in plan view.

6. The device of claim 3 , further comprising:

a fifth conductor provided in a third layer between the base and the fourth conductor, a bottom portion of the first pillar being in contact with the fifth conductor;

a sixth conductor provided in a fourth layer between the base and the fifth conductor; and

a second contact penetrating the first insulating member and the second insulating member, the second contact being provided on the sixth conductor.

7. The device of claim 6 , further comprising:

a third insulating member and a fourth insulating member, each of which is provided to extend in a first direction, the third insulating member and the fourth insulating member sandwiching the first to fourth conductors in a second direction crossing the first direction; and

a fifth insulating member and a sixth insulating member provided between the third insulating member and the fourth insulating member, the fifth insulating member and the sixth insulating member extending in the first direction and being arranged in the second direction, wherein

each of the fifth insulating member and the sixth insulating member includes a portion provided between the first conductor and the first insulating member, and the fifth insulating member and the sixth insulating member are spaced part from each other.

8. The device of claim 6 , further comprising:

a seventh conductor provided in a fifth layer above the second conductor, wherein

each of the first conductor, the second conductor and the fourth conductor includes a portion extending in a first direction,

the first conductor includes a first portion provided on one side in the first direction of the second contact and a second portion provided on the other side in the first direction of the second contact, the first portion of the first conductor and the second portion of the first conductor being electrically connected in the first layer,

the fourth conductor includes a first portion provided on one side in the first direction of the second contact and a second portion provided on the other side in the first direction of the second contact, the first portion of the fourth conductor and the second portion of the fourth conductor being electrically connected in the second layer,

the second conductor includes a first portion provided on one side in the first direction of the second contact and a second portion provided on the other side in the first direction of the second contact, the first portion of the second conductor and the second portion of the second conductor being isolated,

a plurality of first contacts are provided in the first portion and the second portion of the second conductor, and

the first portion and the second portion of the second conductor are electrically connected via the first contacts and the seventh conductor.

9. The device of claim 8 , wherein the seventh conductor includes a crank-shaped pattern which does not overlap the second contact in plan view.

10. The device of claim 8 , wherein

a plurality of second conductors are arranged in a second direction crossing the first direction, and

the plurality of the first contacts with first portions and second portions of the second conductors arranged in the second direction are disposed in a manner to surround the second contact in plan view.

11. The device of claim 1 , further comprising:

a fourth conductor; a third contact; and a fourth contact, wherein

the base includes a first area, a second area and a third area, the first area including the first pillar, and the second area and the third area sandwiching the first area in a first direction,

the fourth conductor is provided in a second layer between the base and the first conductor, the first portion of the first pillar penetrating the fourth conductor,

the third contact is provided on the first conductor in the second area,

the fourth contact is provided on the fourth conductor in the second area, and

the first contact is disposed at a position which is above the fourth conductor and is not above the first conductor in the third area.

12. The device of claim 11 , wherein in the third area, no contact is provided on each of the first conductor and the fourth conductor.

13. The device of claim 11 , wherein in each of the second area and the third area, the first conductor and the fourth conductor are provided in a stepped shape.

14. The device of claim 1 , wherein an area of an upper end of the first portion of the first pillar is greater than an area of a lower end of the second portion of the first pillar.

15. The device of claim 1 , further comprising:

a fourth conductor provided in a second layer between the base and the first conductor, the first portion of the first pillar penetrating the fourth conductor, wherein

the first conductor neighbors the fourth conductor via one insulating layer, and neighbors the second conductor via another insulating layer, and

a distance in a direction of extension of the first pillar is greater between the first conductor and the second conductor than between the first conductor and the fourth conductor.

16. A semiconductor memory device comprising:

a base;

a first conductor provided in a first layer above the base;

a second conductor provided above the first conductor;

a first pillar including a first portion and a second portion formed by different bodies, the first portion of the first pillar being provided to penetrate the first conductor, and the second portion of the first pillar being provided to penetrate the second conductor;

a first insulating member provided at least in the first layer;

a first contact contacting the second conductor above the first insulating member and overlapping the first insulating member in a direction perpendicular to a surface of the base; and

a fourth conductor provided between the base and the first conductor, the first portion of the first pillar penetrating the fourth conductor, wherein

the first insulating member extends in a direction of extension of the first pillar, and penetrates the first conductor and the fourth conductor.

17. The device of claim 16 , wherein an area of an upper end of the first insulating member is greater than an area of a lower end of the first contact.

18. The device of claim 16 , wherein

a plurality of first insulating members penetrate the first conductor and the fourth conductor in the direction of extension of the first pillar,

a plurality of second conductors are provided to extend in a first direction, the second conductors being arranged in a second direction crossing the first direction, and

a plurality of first contacts are provided in contact with the second conductors, respectively, the first contacts being provided above the first insulating members and overlapping the first insulating members in the direction perpendicular to the surface of the base respectively.

19. A semiconductor memory device comprising:

a base;

a first conductor provided in a first layer above the base;

a second conductor provided above the first conductor;

a first pillar including a first portion and a second portion formed by different bodies, the first portion of the first pillar being provided to penetrate the first conductor, and the second portion of the first pillar being provided to penetrate the second conductor;

a first insulating member provided at least in the first layer;

a first contact contacting the second conductor above the first insulating member and overlapping the first insulating member in a direction perpendicular to a surface of the base

a third conductor provided above the second conductor, the second portion of the first pillar being provided to penetrate the third conductor; and

a fifth contact provided in contact with the third conductor, wherein

the base includes a first area and a second area, the first area including the first pillar, the second area neighboring the first area in a first direction and including the first contact and the fifth contact, and the second conductor and the third conductor being provided in a stepped shape in the second area, and

a plurality of first insulating members are provided under the first contact and the fifth contact.

20. The device of claim 19 , wherein

the second conductor neighbors the third conductor via one insulating layer, and neighbors the first conductor via another insulating layer, and

a distance in a direction of extension of the first pillar is greater between the second conductor and the first conductor than between the second conductor and the third conductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2020
From: SUZUKI, YUSAKU; NOJIMA, KAZUHIRO; AIBA, ATSUKO
To: KIOXIA CORPORATION
Reel/Frame 051887/0014 →
Priority Claims (1)
JP JP2019-165432 · Sep 11, 2019 · national
Continuity (1)
Related Publication 20210074711A1 · Mar 11, 2021