Semiconductor memory device

1. A semiconductor memory device comprising:

a substrate including a first area, a second area, a plurality of block regions, and a first dummy block region, the first area and the second area being arranged in a first direction, the block regions each extending in the first direction and being arranged in a second direction intersecting the first direction, and the first dummy block region being adjacent to the block regions in the second direction;

a plurality of insulating members each extending in the first direction, the insulating members being arranged at respective boundary portions of the block regions and the first dummy block region;

a plurality of first conductive layers arranged in a third direction intersecting both the first direction and the second direction and spaced apart from each other, the first conductive layers being partitioned by the insulating members;

a plurality of first pillars penetrating the first conductive layers in a region where the first area and the block regions overlap; and

a plurality of second pillars penetrating at least one of the first conductive layers in a region where the first area and the first dummy block region overlap, wherein

the first conductive layers include, in the first area, a plurality of first terraced portions, each of which does not overlap an upper first conductive layer, and include, in the second area, a plurality of second terraced portions, each of which does not overlap an upper first conductive layer, and

contacts for the first conductive layers are coupled to the second terraced portions, and at least one of the first terraced portions is included in the first dummy block region.

2. The device of claim 1 , wherein

a width of the first dummy block region in the second direction is approximately equal to a width of one of the block regions in the second direction, and

the insulating members are provided on both sides of the first dummy block region.

3. The device of claim 2 , wherein

the first terraced portions are included between the two insulating members provided on the both sides of the first dummy block region.

4. The device of claim 2 , wherein

the substrate further includes a third area, the third area being adjacent to the first dummy block region on an opposite side of the block regions, a width of the third area in the second direction being greater than the width of the first dummy block region in the second direction, and

the insulating members are not included in the third area.

5. The device of claim 2 , wherein

the substrate further includes a third area, the third area being adjacent to the first dummy block region on an opposite side of the block regions, a width of the third area in the second direction being greater than the width of the first dummy block region in the second direction, and

the first terraced portions are not included in the third area.

6. The device of claim 2 , wherein

the substrate further includes a third area, the third area being adjacent to the first dummy block region on an opposite side of the block regions, a width of the third area in the second direction being greater than the width of the first dummy block region in the second direction, and

a pillar similar to the second pillars is not included in the third area.

7. The device of claim 4 , wherein

at least one of the first terraced portions is included in the third area.

8. The device of claim 1 , wherein

the substrate further includes a second dummy block region, the second dummy block region being adjacent to the block regions in the second direction on an opposite side of the first dummy block region, and

the first conductive layers include at least one first conductive layer, the first conductive layer including a terraced portion that does not overlap an upper first conductive layer in a region where the first area and the second dummy block region overlap.

9. The device of claim 1 , wherein

each of the first pillars includes a semiconductor layer and an insulating layer, the semiconductor layer extending in the third direction, the insulting layer covering a side surface of the semiconductor layer, and an intersecting portion of one of the first pillars and one of the first conductive layers functioning as a memory cell, and

on a cross section including one of the first conductive layers and along the first direction and the second direction, the first pillars and the second pillars include a same layer structure.

10. The device of claim 1 , further comprising:

a plurality of third pillars penetrating at least one of the first conductive layers in a region where the second area and the block regions overlap, wherein

on a cross section including one of the first conductive layers and along the first direction and the second direction, the second pillars and the third pillars include a same structure.

11. The device of claim 1 , further comprising:

a plurality of second conductive layers arranged in the third direction and spaced apart from each other between the substrate and the first conductive layers, the second conductive layers being partitioned by the insulating members, wherein

the plurality of second conductive layers include, in the first area, a plurality of third terraced portions, each of which does not overlap an upper second conductive layer, and include, in the second area, a plurality of fourth terraced portions, each of which does not overlap an upper second conductive layer, and

in the first area, one of the first terraced portions and one of the third terraced portions overlap.

12. The device of claim 11 , further comprising:

a plurality of fourth pillars penetrating the second conductive layers in the region where the first area and the block regions overlap, the fourth pillars respectively being coupled to the first pillars; and

a plurality of fifth pillars penetrating at least one of the second conductive layers in the region where the first area and the first dummy block region overlap, wherein

contacts for the second conductive layers are coupled to the fourth terraced portions, and at least one of the third terraced portions is included in the first dummy block region.

13. The device of claim 1 , wherein

each of the first pillars includes a semiconductor layer and an insulating layer, the semiconductor layer extending in the third direction, the insulating layer covering a side surface of the semiconductor layer, and an intersecting portion of at least one of the first pillars and at least one of the first conductive layers functioning as a memory cell,

each of the insulating members includes an insulator and a conductor in the insulator, the insulator expanding in the first direction and the third direction, and the conductor being isolated by the insulator from the first conductive layers in the second direction, and

the conductor is coupled to the semiconductor layer in each of the first pillars through the substrate, and functions as a source line contact.

14. The device of claim 1 , wherein

a number of the second pillars included in the first dummy block region and arranged in the second direction is less than a number of the first pillars included in one of the block regions and arranged in the second direction.

15. A semiconductor memory device comprising:

a substrate including a first area and a second area arranged in a first direction;

a plurality of insulating members each extending in the first direction and being arranged in a second direction intersecting the first direction;

a plurality of first conductive layers arranged in a third direction intersecting both the first direction and the second direction and spaced apart from each other, the first conductive layers including a plurality of region portions partitioned by the insulating members, and the region portions being arranged alternately with the insulating members in the second direction;

a plurality of first pillars penetrating the first conductive layers in the first area; and

a plurality of second pillars, wherein

the first conductive layers include a plurality of first terraced portions, each of which does not overlap an upper first conductive layer, at an end portion in the first area in the second direction, and include a plurality of second terraced portions, each of which does not overlap an upper first conductive layer, in the second area,

contacts for the plurality of first conductive layers are coupled to the second terraced portions, and at least one of the first terraced portions is arranged between two insulating members adjacent in the second direction among the insulating members, and

the plurality of second pillars are provided to penetrate at least one of the first conductive layers in the first terraced portions.

16. The device of claim 15 , wherein

the first pillars and the second pillars are each arranged in staggered rows, and the second pillars are provided at a greater pitch than the first pillars.

17. The device of claim 15 , wherein

on a cross section including one of the first conductive layers and along the first direction and the second direction, a cross-sectional area of the second pillars is greater than a cross-sectional area of the first pillars.

18. The device of claim 15 , further comprising:

a plurality of third pillars penetrating at least one of the first conductive layers in the second terraced portions, wherein

on a cross section including one of the first conductive layers and along the first direction and the second direction, the second pillars and the third pillars include a same structure.

19. The device of claim 18 , wherein

each of the first pillars has a different layer structure from the second pillars and the third pillars on the cross section and includes a semiconductor layer and an insulating layer, the semiconductor layer extending in the third direction, the insulating layer covering a side surface of the semiconductor layer, and an intersecting portion of one of the first pillars and one of the first conductive layers functioning as a memory cell.