Semiconductor device and method of manufacture
A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.
1. A semiconductor device comprising:
a first fin and a second fin extending from a semiconductor substrate;
a gate stack over the first fin and the second fin;
a first gate spacer disposed on sidewalls of the gate stack;
an epitaxial source/drain region in the first fin and the second fin;
a gaseous spacer disposed between the epitaxial source/drain region and the semiconductor substrate and between the first fin and the second fin; and
a first contact etch stop layer (CESL) over the epitaxial source/drain region adjacent the first gate spacer and a first interlayer dielectric (ILD) over the first CESL, wherein a first portion of a boundary of the gaseous spacer is defined by the first CESL.
2. The semiconductor device of claim 1 , wherein a second portion of the boundary of the gaseous spacer is defined by the epitaxial source/drain region.
3. The semiconductor device of claim 2 , wherein a third portion of the boundary of the gaseous spacer is defined by the first gate spacer.
4. The semiconductor device of claim 1 , further comprising a second CESL extending from the first CESL to the first gate spacer, wherein a second portion of the boundary of the gaseous spacer is defined by the second CESL.
5. The semiconductor device of claim 4 , wherein the second CESL comprises silicon nitride.
6. The semiconductor device of claim 5 , wherein the gaseous spacer comprises silane.
7. A semiconductor device comprising:
a fin extending from a substrate;
a gate stack over the fin;
a first gate spacer adjacent the gate stack;
a first source/drain region in the fin adjacent the first gate spacer;
a first contact etch stop layer (CESL) over the first source/drain region;
a first dielectric layer extending from the first gate spacer to the first CESL; and
a gaseous spacer vertically between the first gate spacer and the first dielectric layer.
8. The semiconductor device of claim 7 , wherein the first dielectric layer comprises silicon nitride.
9. The semiconductor device of claim 8 , wherein the gaseous spacer comprises ammonia and silane.
10. The semiconductor device of claim 7 , wherein the gaseous spacer is horizontally between the first gate spacer and the first CESL.
11. The semiconductor device of claim 7 , wherein the gaseous spacer is horizontally between the first gate spacer and the first source/drain region.
12. The semiconductor device of claim 7 , wherein the gaseous spacer contacts opposite side surfaces of the source/drain region.
13. The semiconductor device of claim 7 , wherein the first dielectric layer has a width from 1 nm to 10 nm.
14. A method comprising:
forming a gate stack over a semiconductor substrate;
depositing a first gate spacer layer over the gate stack;
depositing a second gate spacer layer over the first gate spacer layer;
depositing a third gate spacer layer over the second gate spacer layer;
patterning the first gate spacer layer, the second gate spacer layer, and the third gate spacer layer;
epitaxially growing source/drain regions on opposite sides of the gate stack;
removing the second gate spacer layer and the third gate spacer layer to form an opening; and
depositing a dielectric layer sealing the opening and defining a gaseous spacer on sidewalls of the first gate spacer layer.
15. The method of claim 14 , wherein patterning the first gate spacer layer, the second gate spacer layer, and the third gate spacer layer comprises anisotropically etching the first gate spacer layer, the second gate spacer layer, and the third gate spacer layer.
16. The method of claim 14 , further comprising:
depositing a contact etch stop layer (CESL) over the source/drain regions;
depositing an interlayer dielectric layer (ILD) over the CESL; and
planarizing the CESL, the ILD, the gate stack, the first gate spacer layer, and the second gate spacer layer.
17. The method of claim 16 , wherein removing the second gate spacer layer and the third gate spacer layer comprises etching the second gate spacer layer to expose the third gate spacer layer, then etching the third gate spacer layer.
18. The method of claim 14 , wherein the first gate spacer layer comprises silicon carbon nitride, the second gate spacer layer comprises silicon nitride, and the third gate spacer layer comprises silicon oxide.
19. The method of claim 14 , further comprising planarizing the dielectric layer, the gate stack, and the first gate spacer layer.
20. The semiconductor device of claim 4 , wherein a third portion of the boundary of the gaseous spacer is defined by the epitaxial source/drain region, and wherein a fourth portion of the boundary of the gaseous spacer is defined by the first gate spacer.