Semiconductor memory device having a multilayer dielectric structure with a retracted sidewall below a bit line
View Patent ↗A semiconductor memory device includes a substrate, a dielectric layer, plural bit lines, at least one bit line contact, a spacer structure and a spacer layer. The substrate has an isolation area to define plural active areas. The dielectric layer is disposed on the substrate, and the dielectric layer includes a bottom layer having a sidewall being retracted from sidewalls of other layers of the dielectric layer. The plural bit lines are disposed on the dielectric stacked structure, along a direction, and the at least one bit line contact is disposed below one of the bit lines, within the substrate. The spacer structure is disposed at sidewalls of each of the bit lines, and the spacer layer is disposed on the spacer structure to directly in contact with the spacer structure and the other layers of the dielectric layer.
1. A semiconductor memory device, comprising:
a substrate having an isolation area to define a plurality of active areas therein;
a dielectric layer disposed on the substrate, wherein the dielectric layer comprises a multilayer structure and the multilayer structure comprises a bottom layer with a retracted sidewall;
a plurality of bit lines disposed on the dielectric layer, along a direction;
at least one bit line contact disposed in the substrate, below one of the bit lines;
a spacer structure disposed on sidewalls of each of the bit lines; and
a spacer layer disposed on the spacer structure, the spacer layer directly in contact with the spacer structure and other layers of the multilayer structure of the dielectric layer, wherein the spacer layer does not directly contact the bottom layer of the multilayer structure of the dielectric layer.
2. The semiconductor memory device according to claim 1 , wherein the spacer structure comprises a first spacer and a second spacer, and the first spacer and the second spacer comprise different materials.
3. The semiconductor memory device according to claim 2 , wherein the first spacer directly contacts each of the bit lines and two sides of the at least one bit line contact.
4. The semiconductor memory device according to claim 2 , wherein the retracted sidewall of the bottom layer is disposed under the first spacer.
5. The semiconductor memory device according to claim 2 , wherein the spacer layer and the first spacer comprise a same material.
6. The semiconductor memory device according to claim 1 , wherein the retracted sidewall of the bottom layer is disposed under the bit lines.
7. The semiconductor memory device according to claim 1 , wherein the dielectric layer comprises an oxide-nitride-oxide (ONO) structure.
8. The semiconductor memory device according to claim 1 , wherein sidewalls of the spacer structure are vertically aligned with sidewalls of the other layers of the multilayer structure of the dielectric layer.