Library cell modeling for transistor-level test pattern generation

1. A method comprising:

converting, by a computing system, a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell;

generating, by the computing system, test patterns configured to enable detection of target defects injected into the switch-level model of the library cell;

dividing, by the computing system, the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns;

performing, by the computing system, an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to determine which of the test patterns in the second subset of the test patterns enables detection of the target defects when injected into the transistor-level model of the library cell; and

determining, by the computing system, to skip performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.

2. The method of claim 1 , further comprising classifying, by the computing system, the test patterns based on a type of defect detection that is enabled by the test patterns, wherein dividing the test patterns is performed based on the classification.

3. The method of claim 1 , further comprising transforming, by the computing system, the first subset of the test patterns into a fault model format.

4. The method of claim 3 , further comprising:

transforming, by the computing system, the test patterns in the second subset of the test patterns, which were determined to enable detection of the target defects when injected into the transistor-level model of the library cell, into the fault model format; and

combining, by the computing system, the transformed test patterns in the fault model format from the first subset of the test patterns and the second subset of the test patterns into a user-defined fault model file.

5. The method of claim 4 , wherein the user-defined fault model file is configured to allow automatic test equipment to generate test patterns for detection of manufacturing defects in the digital circuit.

6. The method of claim 1 , wherein the transistor-level model of the library cell corresponds to a Simulation Program with Integrated Circuit Emphasis (SPICE) model of the library cell, and wherein the switch-level model of the library cell corresponds to an Automatic Test Pattern Generation (ATPG) model of the library cell.

7. A system comprising:

a memory system configured to store computer-executable instructions; and

a computing system, in response to execution of the computer-executable instructions, is configured to:

convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell;

generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell;

divide the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns;

perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to determine which of the test patterns in the second subset of the test patterns enables detection of the target defects when injected into the transistor-level model of the library cell; and

determine to skip performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.

8. The system of claim 7 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to:

classify the test patterns based on a type of defect detection that is enabled by the test patterns; and

divide the test patterns based on the classification.

9. The system of claim 7 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to transform the first subset of the test patterns into a fault model format.

10. The system of claim 9 , wherein the computing system, in response to execution of the computer-executable instructions, is further configured to:

transform one or more of the test patterns in the second subset of the test patterns, which were determined to enable detection of the target defects when injected into the transistor-level model of the library cell, into the fault model format; and

combine the transformed test patterns in the fault model format from the first subset of the test patterns and the second subset of the test patterns into a user-defined fault model file.

11. The system of claim 10 , wherein the user-defined fault model file is configured to allow automatic test equipment to generate test patterns for detection of manufacturing defects in the digital circuit.

12. An apparatus comprising at least one computer-readable memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

converting a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell;

generating test patterns configured to enable detection of target defects injected into the switch-level model of the library cell;

dividing the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns;

performing an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to determine which of the test patterns in the second subset of the test patterns enables detection of the target defects when injected into the transistor-level model of the library cell; and

determining to skip performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.

13. The apparatus of claim 12 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising classifying the test patterns based on a type of defect detection that is enabled by the test patterns, wherein dividing the test patterns is performed based on the classification.

14. The apparatus of claim 12 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising transforming the first subset of the test patterns into a fault model format.

15. The apparatus of claim 14 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising:

transforming one or more of the test patterns in the second subset of the test patterns, which were determined to enable detection of the target defects when injected into the transistor-level model of the library cell, into the fault model format; and

combining the transformed test patterns in the fault model format from the first subset of the test patterns and the second subset of the test patterns into a user-defined fault model file.

16. The apparatus of claim 15 , wherein the user-defined fault model file is configured to allow automatic test equipment to generate test patterns for detection of manufacturing defects in the digital circuit.

17. The apparatus of claim 12 , wherein the transistor-level model of the library cell corresponds to a Simulation Program with Integrated Circuit Emphasis (SPICE) model of the library cell, and wherein the switch-level model of the library cell corresponds to an Automatic Test Pattern Generation (ATPG) model of the library cell.