Memory cell array circuit and method of forming the same

1. A memory circuit comprising:

a first driver circuit, wherein the first driver circuit comprises:

a first amplifier comprising a first input terminal, a second input terminal and a first output terminal; and

a first transistor comprising a first gate and a first drain, wherein the first gate is coupled to the first output terminal, and the first drain is coupled to the second input terminal;

a first column of memory cells coupled to the first driver circuit;

a first current source;

a tracking circuit configured to track a leakage current of the first column of memory cells, wherein the tracking circuit comprises:

a second driver circuit, and the second driver circuit comprises:

a second amplifier comprising a third input terminal, a fourth input terminal and a second output terminal; and

a second transistor comprising a second gate and a second drain, wherein the second gate is coupled to the second output terminal, and the second drain is coupled to the fourth input terminal; and

a footer circuit coupled to the first column of memory cells, the first current source and the tracking circuit.

2. The memory circuit of claim 1 , wherein the tracking circuit further comprises:

a first column of tracking cells configured to track the leakage current of the first column of memory cells, and coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit.

3. The memory circuit of claim 2 , wherein

the second transistor further comprises a second source, wherein the second drain is further coupled to the first conductive line, and the second source is coupled to a first voltage supply, and the second conductive line being coupled to a second voltage supply different from the first voltage supply.

4. The memory circuit of claim 3 , further comprising:

a third transistor comprising a third gate, a third drain, and a third source, wherein the third gate is coupled to a third output terminal and the second gate, the third drain is coupled to at least a first node, and the third source is coupled to the first voltage supply.

5. The memory circuit of claim 4 , further comprising:

a first transmission gate comprising a first input terminal of the first transmission gate coupled to the third drain by the first node, a second input terminal of the first transmission gate configured to receive a first enable signal, a third input terminal of the first transmission gate configured to receive a second enable signal, and a first output terminal of the first transmission gate coupled to a second node;

a fourth transistor comprising a fourth gate, a fourth drain, and a fourth source, wherein the fourth source is coupled to the first voltage supply; and

a second transmission gate comprising a first input terminal of the second transmission gate coupled to the fourth drain, a second input terminal of the second transmission gate configured to receive a third enable signal, a third input terminal of the second transmission gate configured to receive a fourth enable signal, and a first output terminal of the second transmission gate coupled to at least the second node, the second node being coupled to the footer circuit.

6. The memory circuit of claim 5 , further comprising:

a fifth transistor comprising a fifth gate, a fifth drain, and a fifth source, wherein the fifth source is coupled to the first voltage supply;

a third transmission gate comprising a first input terminal of the third transmission gate coupled to the fifth drain, a second input terminal of the third transmission gate configured to receive a fifth enable signal, a third input terminal of the third transmission gate configured to receive a sixth enable signal, and a first output terminal of the third transmission gate coupled to at least the second node,

wherein each of the second output terminal, the second gate, the third gate, the fourth gate and the fifth gate are coupled together, and

each of the first output terminal of the first transmission gate, the first output terminal of the second transmission gate, the first output terminal of the third transmission gate, and the second node are coupled together.

7. The memory circuit of claim 4 , wherein the footer circuit comprises:

a fourth transistor comprising a fourth gate, a fourth drain, and a fourth source, wherein the fourth drain is coupled to the first node, the third drain, the first current source and the third drain by a third conductive line, and the fourth source is coupled to the second voltage supply; and

a fifth transistor comprising a fifth gate, a fifth drain, and a fifth source, wherein the fifth gate is coupled to the fourth gate and the first current source, the fifth drain is coupled to a first end of a fourth conductive line coupled to the first column of memory cells, the fifth source is coupled to the second voltage supply, and a first current of the fourth drain is equal to a second current of the fifth drain.

8. The memory circuit of claim 3 , further comprising:

a third transistor comprising a third gate, a third drain, and a third source, wherein the third gate is configured to receive a first select signal, the third drain is coupled to a first end of the first conductive line, and the third source is coupled to the second drain and the fourth input terminal; and

a fourth transistor comprising a fourth gate, a fourth drain, and a fourth source, wherein the fourth gate is configured to receive a second select signal, the fourth drain is coupled to a first end of the second conductive line, and the fourth source is coupled to the second voltage supply.

9. The memory circuit of claim 3 , the tracking circuit further comprises:

a second column of tracking cells configured to track another leakage current of a second column of memory cells, and coupled between a third conductive line and a fourth conductive line, the third conductive line being coupled to the second driver circuit and the first conductive line.

10. The memory circuit of claim 1 , wherein the first transistor further comprises a first source, wherein the first drain is further coupled to a first end of a first conductive line of the first column of memory cells, and the first source is coupled to a first voltage supply.

11. A memory circuit comprising:

a first driver circuit, wherein the first driver circuit comprises:

a first amplifier comprising a first input terminal, a second input terminal and a first output terminal; and

a first transistor comprising a first gate and a first drain, wherein the first gate is coupled to the first output terminal, and the first drain is coupled to the second input terminal;

a memory cell array including a first column of memory cells coupled to the first driver circuit;

a second driver circuit;

a first column of tracking cells configured to track a leakage current of the first column of memory cells, and coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit; and

a header circuit coupled to the first driver circuit and the second driver circuit.

12. The memory circuit of claim 11 , wherein the first transistor further comprises a first source, wherein the first drain is further coupled to a first end of a third conductive line of the first column of memory cells, and the first source is coupled to a first voltage supply.

13. The memory circuit of claim 12 , wherein the header circuit comprises:

a second transistor comprising a second gate, a second drain, and a second source, wherein the second gate is coupled to the first output terminal and the first gate, the second drain is coupled to at least a first current path, and the second source is coupled to the first voltage supply; and

a third transistor comprising a third gate, a third drain, and a third source, wherein the third gate is coupled to the second driver circuit, the third drain is coupled to at least a second current path, and the third source is coupled to the first voltage supply.

14. The memory circuit of claim 13 , wherein the second driver circuit comprises:

a second amplifier comprising a first input terminal of the second amplifier, a second input terminal of the second amplifier and a first output terminal of the second amplifier; and

a fourth transistor comprising a fourth gate, a fourth drain, and a fourth source, wherein the fourth gate is coupled to the first output terminal of the second amplifier, the fourth drain is coupled to the second input terminal of the second amplifier and the first conductive line, and the fourth source is coupled to the first voltage supply.

15. The memory circuit of claim 13 , wherein the header circuit further comprises:

a first current mirror coupled to the first current path and the second current path; and

a first current source coupled to the first current path and a first node of the first current mirror.

16. The memory circuit of claim 15 , further comprising:

a fourth transistor comprising a fourth gate, a fourth drain, and a fourth source, wherein the fourth gate is coupled to the second driver circuit and the third gate, the fourth drain is coupled to at least a third current path, and the third source is coupled to the first voltage supply;

a footer circuit coupled to the third current path and a fourth conductive line, the first column of memory cells being coupled between the third conductive line and the fourth conductive line; and

a second current source coupled to the third current path and a first node of footer circuit.

17. The memory circuit of claim 16 , wherein the footer circuit comprises:

a second current mirror coupled to the third current path, the fourth drain and the second current source, and coupled to the fourth conductive line.

18. A memory circuit comprising:

a first driver circuit, wherein the first driver circuit comprises:

a first amplifier comprising a first input terminal of the first amplifier, a second input terminal of the first amplifier and a first output terminal of the first amplifier; and

a first transistor comprising a first gate and a first drain, wherein the first gate is coupled to the first output terminal of the first amplifier, and the first drain is coupled to the second input terminal of the first amplifier;

a first column of memory cells coupled to the first driver circuit;

a second driver circuit;

a first column of tracking cells coupled to the second driver circuit, and configured to track a leakage current of the first column of memory cells, and coupled between a first conductive line and a second conductive line, the first conductive line being coupled to the second driver circuit; and

a header circuit coupled between the first driver circuit and the second driver circuit.

19. The memory circuit of claim 18 , wherein the first transistor further comprises a first source, wherein the first drain is further coupled to a first end of a third conductive line of the first column of memory cells, and the first source is coupled to a first voltage supply,

wherein the first column of memory cells are coupled between the third conductive line and a fourth conductive line.

20. The memory circuit of claim 19 , wherein the header circuit comprises:

a second transistor comprising a second gate, a second drain, and a second source, wherein the second gate is coupled to the first output terminal of the first amplifier and the first gate of the first transistor, the second drain is coupled to at least a first current path, and the second source is coupled to the first voltage supply and the first source of the first transistor;

a third transistor comprising a third gate, a third drain, and a third source, wherein the third gate is coupled to the second driver circuit, the third drain is coupled to at least a second current path, and the third source is coupled to the first voltage supply;

a first current mirror coupled to the first current path, the second drain, the third drain and the second current path; and

a first current source coupled to the first current path and a first node of the first current mirror.