IP Library Granted Patent US 11,637,014
Granted Patent B2
US 11,637,014 · App. 17/064,041 · Granted Apr 25, 2023

Methods for selective deposition of doped semiconductor material

Inventors: Lucas Petersen Barbosa Lima (Heverlee, BE); Rami Khazaka (Leuven, BE); Qi Xie (Wilsele, BE)
Assignee: ASM IP Holding B.V.
H01L21/02579C23C16/455H01L21/02381H01L21/02384H01L21/02488H01L21/02532H01L29/0843
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Quick Facts
Patent No.
US 11,637,014
App. No.
17/064,041
Granted
Apr 25, 2023
Kind
B2
Abstract

Methods and systems for selectively depositing material, such as doped semiconductor material, are disclosed. An exemplary method includes providing a substrate, comprising a first area comprising a first material and a second area comprising a second material, selectively depositing a first doped semiconductor layer overlying the first material relative to the second material and selectively depositing a second doped semiconductor layer overlying the first doped semiconductor layer relative to the second material.

Claims (25)

1. A selective deposition method comprising the steps of:

providing a substrate, comprising a surface comprising a first area comprising a first material and a second area comprising a second material, within a reaction chamber;

selectively and epitaxially depositing a first doped semiconductor layer overlying the first material; and

selectively and epitaxially depositing a second doped semiconductor layer overlying the first doped semiconductor layer;

wherein the first material comprises a doped or undoped monocrystalline material selected from the list consisting of silicon (Si), silicon germanium (SiGe), germanium tin (GeSn), silicon germanium tin (SiGeSn), and germanium (Ge);

wherein the second material comprises a non-monocrystalline dielectric material selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, and mixtures thereof;

wherein the step of selectively depositing the first doped semiconductor layer comprises controlling a pressure of the reaction chamber to be less than 760 Torr; and

wherein one or more of the step of selectively depositing the first doped semiconductor layer or the step of selectively depositing the second doped semiconductor layer comprises repeating a cycle comprising flowing one or more precursors to the reaction chamber and of flowing an etchant to the reaction chamber.

2. The method of claim 1 , wherein the first doped semiconductor layer comprises a lower part and an upper part, wherein the lower part comprises p-type germanium, and wherein the upper part comprises p-type silicon germanium.

3. The method of claim 2 , wherein the p-type germanium comprises boron and gallium doped germanium.

4. The method of claim 3 , wherein the p-type silicon germanium comprises boron-doped silicon germanium.

5. The method of claim 1 , wherein the first doped semiconductor layer has a p-type dopant concentration between 1×10 17 atoms/cm 3 to 5×10 21 atoms/cm 3 .

6. The method according to claim 1 , wherein the second doped semiconductor layer comprises boron-doped silicon.

7. The method according to claim 1 , wherein the second doped semiconductor layer comprises boron and gallium-doped silicon.

8. The method of claim 1 , wherein the step of selectively depositing the first doped semiconductor layer comprises simultaneously flowing a precursor and an etchant to the reaction chamber, wherein the etchant comprises hydrogen chloride and/or chlorine.

9. The method of claim 1 , wherein the etchant comprises a halide gas, wherein the halide gas is selected from the group consisting of hydrogen chloride and chlorine.

10. The method of claim 1 , wherein the step of selectively depositing the first doped semiconductor layer comprises depositing a p-type doped silicon germanium layer, and wherein the step of selectively depositing the second doped semiconductor layer comprises selectively depositing a gallium-doped layer overlying the p-type doped silicon germanium layer.

11. The method of claim 1 , wherein the step of selectively depositing the first doped semiconductor layer comprises heating the substrate to a temperature less than 500° C.

12. The method of claim 1 , wherein during the step of selectively depositing the first doped semiconductor layer, the one or more precursors comprise a silicon-containing precursor, a germanium-containing precursor, and a boron-containing precursor.

13. The method of claim 12 , wherein the silicon-containing precursor, the germanium-containing precursor, and the boron-containing precursor are halide free.

14. The method of claim 13 , wherein the boron-containing precursor comprises at least one of gallium borohydride (Ga(BH 4 ) 3 ), aluminum borohydride (Al(BH 4 ) 3 ), and indium borohydride (In(BH 4 ) 3 ).

15. The method of claim 13 , wherein the boron-containing precursor comprises a borohydride having the formula Y x M(BH 4 ) 3-x , wherein Y is independently chosen from hydrogen, deuterium, chlorine, bromine, and iodine; wherein M is independently chosen from gallium, aluminum, and indium; and wherein x is an integer from 0-2.

16. The method of claim 13 , wherein the boron-containing precursor comprises an organic component, and wherein the first doped semiconductor layer has an atomic percentage of carbon greater than 0.5%.

17. The method of claim 1 , wherein during the step of selectively depositing the second doped semiconductor layer, the one or more precursors comprise a silicon-containing precursor and a gallium-containing precursor.

18. The method of claim 1 , wherein a thickness of the first doped semiconductor layer is between 1 nm and 50 nm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2020
From: PETERSEN BARBOSA LIMA, LUCAS; KHAZAKA, RAMI; XIE, QI
To: ASM IP HOLDING B.V.
Reel/Frame 054129/0731 →
Continuity (2)
Provisional Application 62916662 · Oct 17, 2019
Related Publication 20210118679A1 · Apr 22, 2021