IP Library › Granted Patent US 11,637,084
Granted Patent B2
US 11,637,084 · App. 16/442,873 · Granted Apr 25, 2023

Semiconductor package having a through intervia through the molding compound and fan-out redistribution layers disposed over the respective die of the stacked fan-out system-in-package

Inventors: Chen-Hua Yu (Hsinchu, TW); Kuo-Chung Yee (Taoyuan, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L25/0652H01L21/565H01L21/568H01L21/6835H01L21/76885H01L23/3128H01L24/19H01L24/20H01L24/97H01L25/0655H01L25/0657H01L25/105H01L25/50H01L23/36H01L23/49827H01L23/5389H01L24/16H01L24/17H01L24/94H01L2221/68345H01L2221/68359H01L2224/0231H01L2224/02372H01L2224/02379H01L2224/0401H01L2224/04105H01L2224/05124H01L2224/05147H01L2224/12105H01L2224/16145H01L2224/16227H01L2224/1703H01L2224/32145H01L2224/32225H01L2224/32245H01L2224/73204H01L2224/73253H01L2224/73267H01L2224/81005H01L2224/82005H01L2224/83005H01L2224/8385H01L2224/83191H01L2224/92225H01L2224/92244H01L2224/97H01L2225/06517H01L2225/06527H01L2225/06548H01L2225/06572H01L2225/06586H01L2225/06589H01L2225/1035H01L2225/1041H01L2225/1058H01L2924/01013H01L2924/01029H01L2924/01074H01L2924/1431H01L2924/1436H01L2924/1437H01L2924/1438H01L2924/15311H01L2924/18161H01L2924/18162
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Quick Facts
Patent No.
US 11,637,084
App. No.
16/442,873
Granted
Apr 25, 2023
Kind
B2
Abstract

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

Claims (49)

1. A package comprising:

a first fan-out tier comprising:

a first device die;

a first molding compound extending along sidewalls of the first device die; and

a first through intervia (TIV) extending through the first molding compound;

one or more first fan-out redistribution layers (RDLs) over the first fan-out tier and bonded to the first device die; and

a second fan-out tier over the one or more first fan-out RDLs, wherein the second fan-out tier comprises:

a second device die bonded to the one or more first fan-out RDLs, wherein the one or more first fan-out RDLs electrically connects the first device die to the second device die;

a second molding compound extending along sidewalls of the second device die;

a second TIV extending through the second molding compound; and

a third device die bonded to the one or more first fan-out RDLs, wherein the first device die overlaps the second device die and the third device die in a plan view, and wherein the second TIV is disposed between the second device die and the third device die.

2. The package of claim 1 , further comprising an underfill interposed between the second device die and the one or more first fan-out RDLs.

3. The package of claim 2 , wherein the second molding compound extends along sidewalls of the underfill.

4. The package of claim 1 , wherein the second device die and the third device die are attached directly to the one or more first fan-out RDLs using solder bumps.

5. The package of claim 1 , wherein a front side of the first device die faces a front side of the second device die.

6. The package of claim 1 , further comprising a heat dissipation feature, wherein the second device die is interposed between the heat dissipation feature and the first device die.

7. The package of claim 1 , further comprising one or more second fan-out RDLs below the first fan-out tier and bonded to the first device die.

8. A package comprising:

a first device die;

a first fan-out tier bonded to the first device die, the first fan-out tier comprising:

a second device die, wherein the second device die comprises a through-silicon via (TSV), and wherein the TSV electrically connects the first device die and the second device die;

a first molding compound extending along sidewalls of the second device die; and

a first through intervia (TIV) extending through the first molding compound;

a first fan-out redistribution layer (RDL) bonded to the first fan-out tier; and

a heat dissipation lid attached to a backside of the first device die using an adhesive, the heat dissipation lid being made of a metal layer or a metal alloy layer, the adhesive and the first molding compound having a same width, an entirety of the adhesive being a planar layer, the backside of the first device die facing away from the second device die.

9. The package of claim 8 , further comprising a second TIV extending through the first molding compound.

10. The package of claim 9 , wherein the first TIV and the second TIV do not overlap the first device die in a plan view.

11. The package of claim 8 , further comprising a logic die bonded to the first fan-out RDL, wherein a backside of the logic die faces the first fan-out RDL.

12. The package of claim 11 , wherein the logic die comprises one or more TSVs.

13. The package of claim 8 , further comprising a second molding compound extending along sidewalls of the first device die.

14. The package of claim 8 , further comprising a second fan-out RDL, wherein the second fan-out RDL is interposed between the first device die and the first fan-out tier.

15. The package of claim 8 , wherein a front-side of the second device die faces away from the first device die.

16. A package comprising:

a first redistribution structure;

a first device die over the first redistribution structure, wherein the first device die comprises a first through-silicon via (TSV);

a second redistribution structure over the first device die;

a first molding compound between the first redistribution structure and the second redistribution structure, the first molding compound surrounding the first device die;

a second device die over the second redistribution structure, wherein the second device die comprises a second TSV;

a third redistribution structure over the second device die;

a second molding compound between the second redistribution structure and the third redistribution structure, the second molding compound surrounding the second device die;

a third device die bonded to the first redistribution structure, the first redistribution structure being interposed between the first device die and the third device die;

a first conductive pillar extending through the first molding compound, a first end of the first conductive pillar being level with a first surface of the first molding compound, a second end of the first conductive pillar being level with a second surface of the first molding compound; and

a second conductive pillar extending through the second molding compound, a first end of the second conductive pillar being level with a first surface of the second molding compound, a second end of the second conductive pillar being level with a second surface of the second molding compound.

17. The package of claim 16 , further comprising:

a fourth device die bonded to the third redistribution structure; and

a third molding compound surrounding the fourth device die, wherein the third molding compound is free of conductive pillars.

18. The package of claim 16 , further comprising a fourth device die in the second molding compound, wherein the first device die overlaps the second device die and the fourth device die.

19. The package of claim 16 , further comprising a first connector and a second connector bonded to the first redistribution structure, wherein the third device die is interposed between the first connector and the second connector.

20. The package of claim 16 , further comprising a heat dissipation lid, wherein the first device die and the second device die are interposed between the heat dissipation lid and the third device die.

Continuity (5)
Continuation 16105023 · Aug 20, 2018
Continuation 15464011 · Mar 20, 2017
Continuation 14327203 · Jul 9, 2014
Provisional Application 61981088 · Apr 17, 2014
Related Publication 20190333893A1 · Oct 31, 2019