IP Library Granted Patent US 11,637,147
Granted Patent B2
US 11,637,147 · App. 17/394,091 · Granted Apr 25, 2023

Imaging device

Inventors: Shunsuke Isono (Osaka, JP); Hidenari Kanehara (Kyoto, JP); Sanshiro Shishido (Osaka, JP); Takeyoshi Tokuhara (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
H01L27/307H01L27/14605H01L27/14607H01L27/14636H01L27/14665H04N5/374H04N5/376H01L27/14603H01L27/14612H01L27/14621H01L27/14623H01L27/14627H01L27/14643
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Quick Facts
Patent No.
US 11,637,147
App. No.
17/394,091
Granted
Apr 25, 2023
Kind
B2
Abstract

An imaging device including: a semiconductor substrate including a pixel region and a peripheral region; an insulating layer that covers the pixel and peripheral regions; first electrodes located on the insulating layer above the pixel region; a photoelectric conversion layer that covers the first electrodes; a second electrode that covers the photoelectric conversion layer; detection circuitry configured to be electrically connected to the first electrodes; peripheral circuitry configured to be electrically connected to the detection circuitry, and including analog circuitry; and a third electrode electrically connected to the second electrode. The third electrode overlaps the analog circuitry in a plan view, and in all cross-sections perpendicular to a surface of the semiconductor substrate, parallel to the column direction or the row direction, intersecting at least one of the first electrodes, and intersecting the third electrode, no transistor of the digital circuitry is located directly below the third electrode.

Claims (76)

1. An imaging device comprising:

a semiconductor substrate including a pixel region in which pixels are arranged and a peripheral region adjacent to the pixel region;

an insulating layer that covers the pixel region and the peripheral region;

first electrodes located on the insulating layer above the pixel region and arranged two-dimensionally in a column direction and a row direction;

a photoelectric conversion layer that covers the first electrodes;

a second electrode that covers the photoelectric conversion layer;

detection circuitry located in the pixel region and configured to be electrically connected to the first electrodes;

peripheral circuitry located in the peripheral region, configured to be electrically connected to the detection circuitry, and including analog circuitry and digital circuitry; and

a third electrode located on the insulating layer above the peripheral region, the third electrode being electrically connected to the second electrode, wherein

the third electrode overlaps the analog circuitry in a plan view, and

in all cross-sections perpendicular to a surface of the semiconductor substrate, parallel to the column direction or the row direction, intersecting at least one of the first electrodes, and intersecting the third electrode, no transistor of the digital circuitry is located directly below the third electrode.

2. The imaging device according to claim 1 , wherein

the analog circuitry includes a transistor, and

the third electrode overlaps the transistor in the plan view.

3. The imaging device according to claim 1 , wherein

the peripheral circuitry includes a wire connected between the analog circuitry and the digital circuitry, and

the third electrode overlaps the wire in the plan view.

4. The imaging device according to claim 1 , wherein

the peripheral circuitry includes a wire for connecting the analog circuitry to external circuitry, and

the third electrode overlaps the wire in the plan view.

5. The imaging device according to claim 1 , wherein the third electrode contains the same material as the first electrodes.

6. The imaging device according to claim 1 , wherein a distance between the third electrode and the surface of the semiconductor substrate is the same as a distance between the first electrodes and the surface of the semiconductor substrate.

7. The imaging device according to claim 1 , wherein both of the first electrodes and the third electrode are in direct contact with a top surface of the insulating layer.

8. An imaging device comprising:

a semiconductor substrate including a pixel region in which pixels are arranged and a peripheral region adjacent to the pixel region;

an insulating layer that covers the pixel region and the peripheral region;

first electrodes located on the insulating layer above the pixel region and arranged two-dimensionally in a column direction and a row direction;

a photoelectric conversion layer that covers the first electrodes;

a second electrode that covers the photoelectric conversion layer;

detection circuitry located in the pixel region and configured to be electrically connected to the first electrodes;

peripheral circuitry located in the peripheral region, configured to be electrically connected to the detection circuitry, and including analog circuitry and digital circuitry; and

a third electrode located on the insulating layer above the peripheral region, the third electrode being electrically connected to the second electrode, wherein

the third electrode overlaps the digital circuitry in a plan view, and

in all cross-sections perpendicular to a surface of the semiconductor substrate, parallel to the column direction or the row direction, intersecting at least one of the first electrodes, and intersecting the third electrode, no transistor of the analog circuitry is located directly below the third electrode.

9. The imaging device according to claim 8 , wherein

the analog circuitry includes a transistor, and

the third electrode overlaps the transistor in the plan view.

10. The imaging device according to claim 8 , wherein

the peripheral circuitry includes a wire connected between the analog circuitry and the digital circuitry, and

the third electrode overlaps the wire in the plan view.

11. The imaging device according to claim 8 , wherein

the peripheral circuitry includes a wire for connecting the analog circuitry to external circuitry, and

the third electrode overlaps the wire in the plan view.

12. The imaging device according to claim 8 , wherein the third electrode contains the same material as the first electrodes.

13. The imaging device according to claim 8 , wherein a distance between the third electrode and the surface of the semiconductor substrate is the same as a distance between the first electrodes and the surface of the semiconductor substrate.

14. The imaging device according to claim 8 , wherein both of the first electrodes and the third electrode are in direct contact with a top surface of the insulating layer.

15. An imaging device comprising:

a semiconductor substrate including a pixel region in which pixels are arranged and a peripheral region adjacent to the pixel region;

an insulating layer that covers the pixel region and the peripheral region;

a first electrode located on the insulating layer above the pixel region;

a photoelectric conversion layer that covers the first electrode;

a second electrode that covers the photoelectric conversion layer;

detection circuitry located in the pixel region and connected to the first electrode;

peripheral circuitry located in the peripheral region and connected to the detection circuitry; and

a third electrode located on the insulating layer above the peripheral region, the third electrode being electrically connected to the second electrode, wherein

the third electrode overlaps the peripheral circuitry in a plan view,

the photoelectric conversion layer extends above the peripheral region, and

the photoelectric conversion layer overlaps the peripheral circuitry in the plan view.

16. The imaging device according to claim 15 , wherein

the peripheral circuitry includes a transistor, and

the third electrode overlaps the transistor in the plan view.

17. The imaging device according to claim 15 , wherein

the peripheral circuitry includes analog circuitry connected to the detection circuitry, and

the third electrode overlaps the analog circuitry in the plan view.

18. The imaging device according to claim 17 , wherein

the analog circuitry includes a transistor, and

the third electrode overlaps the transistor in the plan view.

19. The imaging device according to claim 15 , wherein

the peripheral circuitry includes digital circuitry connected to the detection circuitry, and

the third electrode overlaps the digital circuitry in the plan view.

20. The imaging device according to claim 19 , wherein

the digital circuitry includes a transistor, and

the third electrode overlaps the transistor in the plan view.

21. The imaging device according to claim 1 , wherein the third electrode is in direct contact with the second electrode.

22. The imaging device according to claim 8 , wherein the third electrode is in direct contact with the second electrode.

23. The imaging device according to claim 15 , wherein the third electrode is in direct contact with the second electrode.

Priority Claims (1)
JP JP2018-008575 · Jan 23, 2018 · national
Continuity (3)
Continuation 17078440 · Oct 23, 2020
Continuation 16251599 · Jan 18, 2019
Related Publication 20210366992A1 · Nov 25, 2021
Cited By (1)
US 12,495,634