Display panel and display device with completed covered hollowed regions in frame region

1. A display panel, comprising a display region and a frame region surrounding the display region, wherein in the frame region, the display panel includes:

a base substrate;

a planarization layer at a side of the base substrate, wherein:

the planarization layer includes a first region and a second region;

in the first region, a perpendicular distance from an upper surface of the planarization layer to an upper surface of the base substrate is a first distance;

in the second region, a perpendicular distance from an upper surface of the planarization layer to an upper surface of the base substrate is a second distance; and

the first distance is greater than the second distance,

an anode layer at a side of the planarization layer away from the base substrate, wherein:

the anode layer includes a plurality of first hollowed regions and a plurality of second hollowed regions; and

along a direction perpendicular to a plane of the base substrate, the plurality of first hollowed regions at least partially overlaps the first region, and the plurality of second hollowed regions at least partially overlaps the second region,

and

a pixel defining layer at a side of the anode layer away from the base substrate, wherein:

the pixel defining layer includes a plurality of first covering parts and a plurality of second covering parts discrete from each other;

the plurality of first covering parts covers the plurality of first hollowed regions and extends to further cover edges of the anode layer at the plurality of first hollowed regions;

the plurality of second covering parts covers the plurality of second hollowed regions and extends to further cover edges of the anode layer at the plurality of second hollowed regions; and

an area of orthographic projections of the plurality of first covering parts on the base substrate is larger than an area of orthographic projections of the plurality of second covering parts on the base substrate.

2. The display panel according to claim 1 , wherein:

an edge covering width that the plurality of first covering parts covers the anode layer is a 1 ;

an edge covering width that the plurality of second covering parts covers the anode layer is a 2 ; and

a 1 ≥a 2 .

3. The display panel according to claim 2 , wherein 0≤a 1 −a 2 ≤3 μm.

4. The display panel according to claim 1 , wherein:

an edge region of the anode layer close to one of the plurality of first hollowed regions and covered by a corresponding one of the plurality of first covering parts includes a first edge region and a second edge region;

along the direction perpendicular to the plane of the base substrate, the first edge region overlaps the first region and the second edge region overlaps the second region; and

a width of the first edge region is larger than a width of the second edge region.

5. The display panel according to claim 1 , wherein an edge covering width that the plurality of first covering parts covers the anode layer is a 1 , wherein 1 μm≤a 1 ≤5 μm.

6. The display panel according to claim 1 , wherein:

the first region includes a first side edge and a second side edge opposite to each other along a first direction; and

along the direction perpendicular to the plane of the base substrate, orthographic projections of the plurality of first hollowed regions completely cover the first side edge and the second side edge.

7. The display panel according to claim 1 , wherein an area of the plurality of first hollowed regions is larger than an area of the plurality of second hollowed regions.

8. The display panel according to claim 1 , further including an array layer between the base substrate and the planarization layer, wherein the array layer includes:

a semiconductor layer on the base substrate;

a gate insulating layer on a side of the semiconductor layer away from the base substrate;

a first metal layer on a side of the gate insulating layer away from the base substrate;

an interlayer dielectric layer on a side of the first metal layer away from the base substrate;

a second metal layer on a side of the interlayer dielectric layer away from the base substrate;

a passivation layer on a side of the second metal layer away from the base substrate; and

a third metal layer on a side of the passivation layer away from the base substrate, wherein the second metal layer overlaps the third metal layer in the first region.

9. The display panel according to claim 8 , wherein:

the frame region includes a driving circuit disposed in the array layer;

the driving circuit includes a plurality of driving signal lines; and

along the direction perpendicular to the plane of the base substrate, a thickness of the plurality of driving signal lines in the first region is larger than a thickness of the plurality of driving signal lines in the second region.

10. The display panel according to claim 8 , wherein:

the frame region includes clock signal lines in the first region;

the clock signal lines include a first sub clock signal line disposed in the second metal layer and a second sub clock signal line in the third metal layer; and

the first sub clock signal line and the second sub clock signal line are configured in parallel.

11. The display panel according to claim 10 , wherein:

the first sub clock signal line and the second sub clock signal line are electrically connected to each other by a direct contact.

12. The display panel according to claim 10 , wherein:

the first sub clock signal line and the second sub clock signal line are electrically connected to each other through at least two through holes.

13. The display panel according to claim 1 , wherein:

the anode layer includes a plurality of sub anode layers configured in a multilayer stacking structure along the direction perpendicular to the plane of the base substrate.

14. The display panel according to claim 13 , wherein:

the plurality of sub anode layers includes a first sub anode layer, a second sub anode layer, and a third sub anode layer disposed sequentially along a direction from the base substrate to the anode layer;

the first sub anode layer and the third sub anode layer are transparent conductive oxide layers;

the second sub anode layer is a metal sub layer; and

the plurality of first covering parts covers the metal sub layer of the anode layer close to the side edges of the plurality of first hollowed regions.

15. The driving panel according to claim 14 , wherein:

the transparent conductive oxide layers include indium doped tin oxide (ITO) layers; and

the metal sub layer includes a silver layer.

16. A display device, comprising a display panel, wherein:

the display panel includes a display region and a frame region surrounding the display region; and

in the frame region, the display panel includes:

a base substrate;

a planarization layer at a side of the base substrate, wherein:

the planarization layer includes a first region and a second region;

in the first region, a perpendicular distance from an upper surface of the planarization layer to an upper surface of the base substrate is a first distance;

in the second region, a perpendicular distance from an upper surface of the planarization layer to an upper surface of the base substrate is a second distance; and

the first distance is larger than the second distance,

an anode layer at a side of the planarization layer away from the base substrate, wherein:

the anode layer includes a plurality of first hollowed regions and a plurality of second hollowed regions; and

along a direction perpendicular to a plane of the base substrate, the plurality of first hollowed regions at least partially overlaps the first region, and the plurality of second hollowed regions at least partially overlaps the second region,

and

a pixel defining layer at a side of the anode layer away from the base substrate, wherein:

the pixel defining layer includes a plurality of first covering parts and a plurality of second covering parts which are discrete from each other;

the plurality of first covering parts covers the plurality of first hollowed regions and extends to further cover edges of the anode layer at the plurality of first hollowed regions;

the plurality of second covering parts covers the plurality of second hollowed regions and extends to further cover edges of the anode layer at the plurality of second hollowed regions; and

an area of orthographic projections of the plurality of first covering parts on the base substrate is larger than an area of orthographic projections of the plurality of second covering parts on the base substrate.