Semiconductor device
A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.
1. A semiconductor device, comprising:
a substrate;
a channel pattern on the substrate, the channel pattern including a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern sequentially stacked on the substrate;
a source/drain pattern on the substrate and connected to the channel pattern; and
a gate electrode on the channel pattern, the gate electrode including a first portion between the substrate and the first semiconductor pattern, a second portion between the first semiconductor pattern and the second semiconductor pattern, and a third portion between the second semiconductor pattern and the third semiconductor pattern,
wherein the first portion includes a first sidewall facing the source/drain pattern,
wherein the third portion includes a second sidewall facing the source/drain pattern, and
wherein one of the first and second sidewalls has a positive slope and the other has a negative slope.
2. The semiconductor device of claim 1 , further comprising a gate dielectric layer between the gate electrode and the channel pattern,
wherein gate dielectric layer includes a first gate dielectric pattern between the source/drain pattern and the first portion, a second gate dielectric pattern between the source/drain pattern and the second portion, and a third gate dielectric pattern between the source/drain pattern and the third portion,
wherein the first gate dielectric pattern includes a third sidewall in contact with the source/drain pattern,
wherein the third gate dielectric pattern includes a fourth sidewall in contact with the source/drain pattern, and
wherein one of the third and fourth sidewalls has a positive slope and the other has a negative slope.
3. The semiconductor device of claim 1 , wherein a maximum width of the first portion is greater than a maximum width of the second portion,
wherein the maximum width of the first portion is greater than a maximum width of the third portion, and
wherein the maximum width of the second portion is different from the maximum width of the third portion.
4. The semiconductor device of claim 1 , wherein the source/drain pattern includes a lower portion in contact with the substrate and adjacent to the first portion,
wherein a width of the lower portion decreases with decreasing distance from a bottom surface of the substrate.
5. The semiconductor device of claim 4 , wherein an interface between the lower portion and the substrate has a rounded shape.
6. The semiconductor device of claim 1 , wherein the first sidewall has the positive slope, such that a first length of a bottom of the first portion is greater than a second length of a top of the first portion, and
wherein the second sidewall has the negative slope, such that a third length of a bottom of the third portion is smaller than a fourth length of a top of the third portion.
7. The semiconductor device of claim 1 , wherein the channel pattern, the source/drain pattern and the gate electrode are on a PMOSFET region of the substrate.
8. A semiconductor device, comprising:
a substrate;
a channel pattern on the substrate, the channel pattern including a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern sequentially stacked on the substrate;
a first source/drain pattern and a second source/drain pattern that are on the substrate, the channel pattern being between the first and second source/drain patterns;
a gate electrode on the channel pattern, the gate electrode including a first portion between the substrate and the first semiconductor pattern, a second portion between the first semiconductor pattern and the second semiconductor pattern, and a third portion between the second semiconductor pattern and the third semiconductor pattern;
a first barrier insulating pattern between the first portion and the first source/drain pattern; and
a second barrier insulating pattern between the first portion and the second source/drain pattern,
wherein the first barrier insulating pattern includes a first sidewall in contact with the first source/drain pattern,
wherein the second barrier insulating pattern includes a second sidewall in contact with the second source/drain pattern, and
wherein a first distance between the first sidewall and the second sidewall increases with decreasing distance from a bottom surface of the substrate.
9. The semiconductor device of claim 8 , further comprising
a third barrier insulating pattern between the third portion and the first source/drain pattern; and
a fourth barrier insulating pattern between the third portion and the second source/drain pattern,
wherein the third barrier insulating pattern includes a third sidewall in contact with the first source/drain pattern,
wherein the fourth barrier insulating pattern includes a fourth sidewall in contact with the second source/drain pattern, and
wherein a second distance between the third sidewall and the fourth sidewall is smaller than the first distance.
10. The semiconductor device of claim 8 , wherein a second distance between the first and second source/drain patterns measured at a level where the first portion is located is greater than a third distance between the first and second source/drain patterns measured at a level where the third portion is located.
11. The semiconductor device of claim 8 , wherein the first source/drain pattern includes a lower portion in contact with the substrate and adjacent to the first portion,
wherein a width of the lower portion decreases with decreasing distance from the bottom surface of the substrate.
12. The semiconductor device of claim 11 , wherein an interface between the lower portion and the substrate has a rounded shape.
13. The semiconductor device of claim 8 , wherein a first length of a bottom of the first barrier pattern is greater than a second length of a top of the first barrier pattern.
14. The semiconductor device of claim 13 , wherein the bottom of the first barrier pattern is in contact with the substrate, and
wherein the top of the first barrier pattern is in contact with the first semiconductor pattern.
15. The semiconductor device of claim 8 , further comprising a gate dielectric layer between the gate electrode and the channel pattern,
wherein the gate dielectric layer includes a first gate dielectric pattern between the first barrier insulating pattern and the first portion, and
wherein the gate dielectric layer includes a second gate dielectric pattern between the second barrier insulating pattern and the first portion.
16. The semiconductor device of claim 8 , wherein the channel pattern, the first and second source/drain patterns and the gate electrode are on a NMOSFET region of the substrate.
17. A semiconductor device, comprising:
a substrate including a PMOSFET region;
a channel pattern on the PMOSFET region, the channel pattern including a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern sequentially stacked on the substrate;
a source/drain pattern on the PMOSFET region and connected to the channel pattern; and
a gate electrode on the channel pattern, the gate electrode including a first portion between the substrate and the first semiconductor pattern, a second portion between the first semiconductor pattern and the second semiconductor pattern, and a third portion between the second semiconductor pattern and the third semiconductor pattern,
wherein a width of the first portion increases with decreasing distance from a bottom surface of the substrate.
18. The semiconductor device of claim 17 , wherein a maximum width of the first portion is greater than a maximum width of the second portion,
wherein the maximum width of the first portion is greater than a maximum width of the third portion, and
wherein the maximum width of the second portion is different from the maximum width of the third portion.
19. The semiconductor device of claim 17 , wherein a width of the third portion decreases with decreasing distance from the bottom surface of the substrate.
20. The semiconductor device of claim 17 , wherein the source/drain pattern includes a lower portion in contact with the substrate and adjacent to the first portion, and
wherein an interface between the lower portion and the substrate has a rounded shape, such that a width of the lower portion decreases with decreasing distance from the bottom surface of the substrate.