Quasi-cyclic LDPC coding and decoding method and apparatus, and LDPC coder and decoder
A quasi-cyclic LDPC coding and decoding method and apparatus, and an LDPC coder and decoder. The method includes: determining from a mother basis matrix set a basis matrix used for low density parity check (LDPC) coding (S 202 ), wherein the basis matrix used for LDPC coding includes a first-type element and a second-type element, the first-type element corresponds to an all-zero square matrix, the second-type element corresponds to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and dimensions of the all-zero square matrix and the unit matrix are equal; and performing LDPC coding on an information sequence to be coded according to the basis matrix used for LDPC coding, and/or performing LDPC decoding on a data sequence to be decoded according to the basis matrix used for LDPC coding (S 204 ).
1. A quasi-cyclic LDPC encoding or decoding method comprising:
determining a basic matrix used for low density parity check (LDPC) coding from a mother basic matrix set, wherein the basic matrix used for LDPC coding comprises a first-type element corresponding to an all-zero square matrix and a second-type element corresponding to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and wherein dimensions of the all-zero square matrix and the unit matrix are equal; and
performing LDPC coding on an information sequence to be coded according to the basic matrix used for LDPC coding,
wherein the mother basic matrix set comprises A4 basic matrix subsets and each basic matrix subset comprises S basic matrices, wherein A4 is an integer greater than 1 and S is an integer that is greater than or equal to 3, and wherein positions of the second-type element of all of the S basic matrices in a same basic matrix subset are same.
2. The method of claim 1 , wherein determining the basic matrix used for the LDPC coding from the mother basic matrix set comprises:
determining the basic matrix used for the LDPC coding based on a preset parameter, wherein the preset parameter comprises a combination of a transport block size TBS and a code rate R, wherein the transport block size TBS is an integer that is greater than 0, and wherein the code rate R is a real number which is greater than 0 and less than 1.
3. The method of claim 1 , wherein determining the basic matrix used for the LDPC coding from the mother basic matrix set comprises:
determining the basic matrix used for the LDPC coding based on a preset parameter, wherein the preset parameter comprises a combination of a modulation and coding scheme MCS index number and a number of resource units NRB, wherein the MCS index number is used to indicate an MCS scheme, and wherein the number of resource units NRB is a number of system-configured resource blocks.
4. The method of claim 1 , wherein determining the basic matrix used for the LDPC coding from the mother basic matrix set comprises:
determining the basic matrix used for the LDPC coding based on a preset parameter, wherein the preset parameter comprises a combination of a code rate R and a number of resource units NRB, wherein the code rate R is a real number which is greater than 0 and less than 1, and wherein the number of resource units NRB is a number of system-configured resource blocks.
5. The method of claim 1 , wherein parameters of an i th basic matrix subset of the A4 basic matrix subsets include a matrix column number of NBi, a matrix row number of MBi, and a matrix system column number of KBi, where i=0, 1, . . . , (A4-1), and wherein MBi is an integer greater than 0, NBi is an integer greater than MBi, KBi=NBi-MBi.
6. The method of claim 1 , wherein code rates supported by all of the S basic matrices in a same basic matrix subset are same.
7. The method of claim 1 , wherein all of the S basic matrices in a same basic matrix subset support different code lengths.
8. An apparatus for quasi-cyclic LDPC encoding or decoding, comprising:
a processor configured to:
determine a basic matrix used for low density parity check (LDPC) coding from a mother basic matrix set, wherein the basic matrix used for LDPC coding comprises a first-type element corresponding to an all-zero square matrix and a second-type element corresponding to a matrix obtained by means of a cyclic shift of a unit matrix according to a value of the second-type element, and wherein dimensions of the all-zero square matrix and the unit matrix are equal; and
perform LDPC coding on an information sequence to be coded according to the basic matrix used for LDPC coding,
wherein the mother basic matrix set comprises A4 basic matrix subsets and each basic matrix subset comprises S basic matrices, wherein A4 is an integer greater than 1 and S is an integer that is greater than or equal to 3, and wherein positions of the second-type element of all of the S basic matrices in a same basic matrix subset are same.
9. The apparatus of claim 8 , wherein the processor is further configured, as part of determining the basic matrix used for the LDPC coding from the mother basic matrix set, to:
determine the basic matrix used for the LDPC coding based on a preset parameter, wherein the preset parameter comprises a combination of a transport block size TBS and a code rate R, wherein the transport block size TBS is an integer that is greater than 0, and wherein the code rate R is a real number which is greater than 0 and less than 1.
10. The apparatus of claim 8 , wherein the processor is further configured, as part of determining the basic matrix used for the LDPC coding from the mother basic matrix set, to:
determine the basic matrix used for the LDPC coding based on a preset parameter, wherein the preset parameter comprises a combination of a modulation and coding scheme MCS index number and a number of resource units NRB, wherein the MCS index number is used to indicate an MCS scheme, and wherein the number of resource units NRB is a number of system-configured resource blocks.
11. The apparatus of claim 8 , wherein the processor is further configured, as part of determining the basic matrix used for the LDPC coding from the mother basic matrix set, to:
determine the basic matrix used for the LDPC coding based on a preset parameter, wherein the preset parameter comprises a combination of a code rate R and a number of resource units NRB, wherein the code rate R is a real number which is greater than 0 and less than 1, and wherein the number of resource units NRB is a number of system-configured resource blocks.
12. The apparatus of claim 8 , wherein parameters of an i th basic matrix subset of the A4 basic matrix subsets comprise a matrix column number of NBi, a matrix row number of MBi, and a matrix system column number of KBi, where i=0, 1, . . . , (A4-1), and wherein MBi is an integer greater than 0, NBi is an integer greater than MBi, KBi=NBi-MBi.
13. The apparatus of claim 8 , wherein code rates supported by all of the S basic matrices in a same basic matrix subset are same.
14. The apparatus of claim 8 , wherein all of the S basic matrices in a same basic matrix subset support different code lengths.