Method and apparatus of rate-matching for communication and broadcasting systems
A communication method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The method and apparatus for polar encoding and rate-matching are disclosed.
1. A method performed by a transmitter in a communication system, the method comprising:
identifying a first bit sequence to be encoded, the first bit sequence including an information bit sequence and cyclic redundancy check (CRC) bits for the information bit sequence;
identifying a second bit sequence by encoding the first bit sequence with a polar code;
identifying a third bit sequence by performing an interleaving on the second bit sequence based on an interleaving pattern;
performing a rate matching on the third bit sequence by determining one of a repetition or a puncturing or a shortening as the rate matching, based on a length of the first bit sequence, a length of the second bit sequence, and a length of a rate matching output sequence; and
obtaining the rate matching output sequence by performing the rate matching,
wherein the interleaving pattern corresponds to {0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31}.
2. The method of claim 1 ,
wherein the third bit sequence includes a plurality of subblocks, of the second bit sequence, which are rearranged based on the interleaving pattern, and
wherein a number of the plurality of subblocks is 32.
3. The method of claim 1 , wherein the interleaving pattern is determined based on a partial order.
4. The method of claim 1 , wherein the second bit sequence includes one or more bit, to be rated matched, set as 0.
5. The method of claim 1 ,
wherein in case that the length of the rate matching output sequence is shorter than the length of the second bit sequence, one of the puncturing or the shortening is determined as the rate matching based on a code rate which is determined based on the length of the first bit sequence and the length of the rate matching output sequence, and
wherein in case that the length of the rate matching output sequence is longer than the length of the second bit sequence, the repetition is determined as the rate matching.
6. The method of claim 1 ,
wherein the performing the rate matching comprises:
storing the third bit sequence in a circular buffer; and
performing the puncturing of a former portion of bits in the third bit sequence, and
wherein a length of the former portion of the bits is determined by subtracting the length of the rate matching output sequence from the length of the second bit sequence.
7. The method of claim 1 ,
wherein the performing the rate matching comprises:
storing the third bit sequence in a circular buffer; and
performing the shortening of a latter portion of bits of the third bit sequence, and
wherein a length of the latter portion of the bits is determined by subtracting the length of the rate matching output sequence from the length of the second bit sequence.
8. The method of claim 1 ,
wherein the performing the rate matching comprises:
storing the third bit sequence in a circular buffer; and
performing the repetition of bits in the third bit sequence, and
wherein a length of the bits to be repeated is determined by subtracting the length of the second bit sequence from the length of the rate matching output sequence.
9. An apparatus in a communication system, the apparatus comprising:
a transceiver; and
a controller coupled with the transceiver and configured to:
identify a first bit sequence to be encoded, the first bit sequence including an information bit sequence and cyclic redundancy check (CRC) bits for the information bit sequence,
identify a second bit sequence by encoding the first bit sequence with a polar code,
identify a third bit sequence by performing an interleaving on the second bit sequence based on an interleaving pattern,
perform a rate matching on the third bit sequence by determining one of a repetition or a puncturing or a shortening as the rate matching, based on a length of the first bit sequence, a length of the second bit sequence, and a length of a rate matching output sequence, and
obtain the rate matching output sequence by performing the rate matching,
wherein the interleaving pattern corresponds to {0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31}.
10. The apparatus of claim 9 ,
wherein the third bit sequence includes a plurality of subblocks, of the second bit sequence, which are rearranged based on the interleaving pattern, and
wherein a number of the plurality of subblocks is 32.
11. The apparatus of claim 9 , wherein the interleaving pattern is determined based on a partial order.
12. The apparatus of claim 9 , wherein the second bit sequence includes one or more bit, to be rated matched, set as 0.
13. The apparatus of claim 9 ,
wherein in case that the length of the rate matching output sequence is shorter than the length of the second bit sequence, one of the puncturing or the shortening is determined as the rate matching based on a code rate which is determined based on the length of the first bit sequence and the length of the rate matching output sequence, and
wherein in case that the length of the rate matching output sequence is longer than the length of the second bit sequence, the repetition is determined as the rate matching.
14. The apparatus of claim 9 ,
wherein to perform the rate matching, the controller is further configured to:
store the third bit sequence in a circular buffer, and
perform the puncturing of a former portion of bits in the third bit sequence, and
wherein a length of the former portion of the bits is determined by subtracting the length of the rate matching output sequence from the length of the second bit sequence.
15. The apparatus of claim 9 ,
wherein to perform the rate matching, the controller is further configured to:
store the third bit sequence in a circular buffer, and
perform the shortening of a latter portion of bits of the third bit sequence, and
wherein a length of the latter portion of the bits is determined by subtracting the length of the rate matching output sequence from the length of the second bit sequence.
16. The apparatus of claim 9 ,
wherein to perform the rate matching, the controller is further configured to:
store the third bit sequence in a circular buffer, and
perform the repetition of bits in the third bit sequence, and
wherein a length of the bits to be repeated is determined by subtracting the length of the second bit sequence from the length of the rate matching output sequence.