Semiconductor devices including metal gate protection and methods of fabrication thereof
Embodiments of the present disclosure provide semiconductor device structures. In one embodiment, the semiconductor device structure includes a gate dielectric layer, a gate electrode layer in contact with the gate dielectric layer, a first self-aligned contact (SAC) layer disposed over the gate electrode layer, an isolation layer disposed between the gate electrode layer and the first SAC layer, and a first sidewall spacer in contact with the gate dielectric layer, the isolation layer, and the first SAC layer.
1. A semiconductor device structure, comprising:
a gate dielectric layer;
a gate electrode layer in contact with the gate dielectric layer;
a first self-aligned contact (SAC) layer disposed over the gate electrode layer;
an isolation layer disposed over the gate electrode layer;
a metal layer disposed between and in contact with the gate electrode layer and the isolation layer; and
a first sidewall spacer in contact with the gate dielectric layer, the isolation layer, and the first SAC layer.
2. The semiconductor device structure of claim 1 , wherein the isolation layer is formed of a dielectric material free of oxygen atoms.
3. The semiconductor device structure of claim 1 , wherein the isolation layer is in contact with the first SAC layer.
4. The semiconductor device structure of claim 1 , wherein the metal layer is further in contact with the gate dielectric layer.
5. The semiconductor device structure of claim 1 , wherein the first sidewall spacer is in contact with the metal layer.
6. The semiconductor device structure of claim 5 , further comprising:
a second sidewall spacer in contact with the first sidewall spacer.
7. The semiconductor device structure of claim 6 , further comprising:
a contact etch stop layer (CESL) in contact with the second sidewall spacer and the first SAC layer.
8. The semiconductor device structure of claim 7 , further comprising:
a source/drain metal contact disposed adjacent the CESL; and
a second self-aligned contact (SAC) layer in contact with the source/drain metal contact and the CESL.
9. A semiconductor device structure, comprising:
first and second source/drain features;
a channel layer disposed between and in contact with the first and second source/drain features, wherein the channel layer is formed of a semiconductor layer;
a gate dielectric layer surrounding at least a surface of the channel layer;
a gate electrode layer surrounding at least a surface of the gate dielectric layer;
a first self-aligned contact (SAC) layer disposed over the gate electrode layer, wherein the SAC layer comprises a dielectric material;
an isolation layer disposed over the gate electrode layer;
a metal layer disposed between and in contact with the gate electrode layer and the isolation layer; and
a first sidewall spacer in contact with the gate dielectric layer, the first SAC layer, and the isolation layer.
10. The semiconductor device structure of claim 9 , wherein the isolation layer is formed of a dielectric material free of oxygen atoms.
11. The semiconductor device structure of claim 9 , further comprising:
a second sidewall spacer in contact with the first sidewall spacer and the first SAC layer.
12. The semiconductor device structure of claim 11 , further comprising:
a source/drain metal contact disposed over the first and second source/drain features;
a second self-aligned contact (SAC) layer in contact with the source/drain metal contact; and
a contact etch stop layer (CESL) disposed between and in contact with the second SAC and the first SAC layer.
13. The semiconductor device structure of claim 9 , further comprising:
a liner layer in contact with the gate electrode layer.
14. The semiconductor device structure of claim 13 , wherein the liner layer is formed of a dielectric material free of oxygen atoms.
15. The semiconductor device structure of claim 13 , further comprising:
a second sidewall spacer in contact with the first sidewall spacer and the liner layer; and
a contact etch stop layer (CESL) in contact with the liner layer and the second sidewall spacer.
16. The semiconductor device structure of claim 15 , further comprising:
a source/drain metal contact disposed over the first and second source/drain features; and
a second self-aligned contact (SAC) layer in contact with the source/drain metal contact.
17. A method for forming a semiconductor device structure, comprising:
forming a fin structure having a plurality of channel layers disposed thereover;
forming a sacrificial gate structure over a portion of the fin structure;
forming a sidewall spacer on opposing sides of the sacrificial gate structure;
removing the sacrificial gate structure to expose portions of the plurality of channel layers;
forming a gate dielectric layer on exposed portions of the plurality of channel layers;
forming a gate electrode layer on the gate dielectric layer;
removing portions of the gate electrode layer and the gate dielectric layer so that top surfaces of the gate electrode layer and the gate dielectric layer are lower than a top surface of the sidewall spacer;
forming a metal layer over the gate electrode layer;
forming an isolation layer over the gate electrode layer and the gate dielectric layer, wherein the isolation layer comprises a dielectric material free of oxygen atoms; and
forming a self-aligned contact (SAC) layer on the isolation layer.
18. The method of claim 17 , wherein the metal layer is disposed between and in contact with the gate electrode layer and the isolation layer.