III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts

1. An integrated circuit structure, comprising:

a lower device layer that includes a first structure comprising a plurality of PMOS transistors, wherein respective ones of the plurality of PMOS transistors comprise:

a gate electrode formed on a gate dielectric layer formed on a silicon layer;

a pair of sidewall spacers formed along opposite sides of the gate electrode; and

a pair of source/drain regions formed on opposite sides of and extending beneath the gate electrode;

a bonding layer material formed on the lower device layer; and

an upper device layer formed on the bonding layer material, the upper device layer including a second structure comprising a plurality of NMOS transistors, wherein respective ones of the plurality of NMOS transistors comprise:

a gate electrode formed on a gate dielectric layer formed on a fin;

a pair of sidewall spacers formed along opposite sides of the gate electrode;

a group III-V material source/drain region formed on opposite sides of and extending beneath the gate electrode, and wherein the a group III-V material source/drain region is formed adjacent to the sidewall spacers and above a bottom surface of the gate dielectric layer, wherein the pair of sidewall spacers provide 2-5 nm of lateral spacing between gate electrode and group III-V material source/drain region; and

a metal contact directly contacting the group III-V material source/drain region, wherein source/drain region has a contact resistivity between approximately 3e-10 and 1e-8 Ω-cm 2 .

2. The integrated circuit structure of claim 1 , wherein the plurality of NMOS transistors are non-planar.

3. The integrated circuit structure of claim 1 , wherein the bonding layer material comprises an oxide layer.

4. The integrated circuit structure of claim 1 , wherein the plurality of PMOS transistors are non-planar.

5. The integrated circuit structure of claim 1 , wherein the second plurality of NMOS transistors are formed as at least one of multi-gate transistors, vertical circular gate (CG) transistors, and nanowire transistors.

6. The integrated circuit structure of claim 1 , wherein the plurality of PMOS transistors are formed as at least one of multi-gate transistors, vertical circular gate (CG) transistors, and nanowire transistors.

7. The integrated circuit structure of claim 1 , wherein both the second plurality of NMOS transistors are formed as a same type of transistor architecture including at least one of finFET, multi-gate, vertical circular gate (CG), and nanowire.

8. The integrated circuit structure of claim 1 , wherein the group III-V material source/drain region comprises a narrow band gap alloy of indium gallium arsenide (In x Ga y As y ).

9. The integrated circuit structure of claim 1 , wherein the group III-V material source/drain region comprises one of: indium arsenide (InAs), indium antimony (InSb), indium arsenide antimony (InAsSb), gallium arsenide (GaAs), gallium arsenide antimony (GaAsSb), indium phosphorus (InP).

10. The integrated circuit structure of claim 1 , wherein the plurality of NMOS transistors are formed as at least one of multi-gate transistors, vertical circular gate (CG) transistors, and nanowire transistors.

11. The integrated circuit structure of claim 1 , wherein the plurality of PMOS transistors are formed as at least one of multi-gate transistors, vertical circular gate (CG) transistors, and nanowire transistors.

12. The integrated circuit structure of claim 1 , wherein the plurality of NMOS transistors and the plurality of PMOS transistors are formed as a same type of transistor architecture including at least one of finFET, multi-gate, vertical circular gate (CG), and nanowire.

13. A method of fabricating an integrated device structure comprising a vertically stacked transistor device architecture, the method comprising:

forming a lower device layer that includes a first structure comprising a plurality of PMOS transistors, wherein respective ones of the plurality of PMOS transistors comprise:

a gate electrode formed on a gate dielectric layer formed on a silicon layer;

a pair of sidewall spacers formed along opposite sides of the gate electrode; and

a pair of source/drain regions formed on opposite sides of and extending beneath the gate electrode;

forming a bonding layer material formed on the lower device layer; and

forming an upper device layer formed on the bonding layer material, the upper device layer including a second structure comprising a plurality of NMOS transistors, wherein respective ones of the plurality of NMOS transistors comprise:

a gate electrode formed on a gate dielectric layer formed on a fin;

a pair of sidewall spacers formed along opposite sides of the gate electrode; and

a group III-V material source/drain region formed on opposite sides of and extending beneath the gate electrode, and wherein the a group III-V material source/drain region is formed adjacent to the sidewall spacers and above a bottom surface of the gate dielectric layer, wherein the pair of sidewall spacers provide 2-5 nm of lateral spacing between gate electrode and group III-V material source/drain region; and

a metal contact directly contacting the group III-V material source/drain region, wherein source/drain region has a contact resistivity between approximately 3e-10 and 3e-10 and 1e-8 Ω-cm 2.

14. The method of claim 13 , further comprising forming ones of the plurality of NMOS transistors by:

etching silicon from the bonding layer material to form a silicon fin;

patterning a channel mask to protect a portion of the fin that is to become the channel region;

recess etching portions of the fin not protected by the channel mask to form recesses;

epitaxially growing the III-V semiconductor material on surfaces of the fin not protected by the channel mask; and

replacing the channel mask with a permanent gate stack and forming contact metallization.

15. The method of claim 14 , wherein epitaxially growing the III-V semiconductor material further comprises epitaxially growing at least one of In x Ga y As y , indium arsenide (InAs), indium antimony (InSb), indium arsenide antimony (InAsSb), gallium arsenide (GaAs), gallium arsenide antimony (GaAsSb), indium phosphorus (InP).