Electronic device including memory device and training method
An electronic device includes a memory device receiving a power supply voltage, a data strobe signal, and a data signal, and a system-on-chip that exchanges data with the memory device using the data strobe signal and the data signal. The system-on-chip performs write training that measures a magnitude of a delay of the data strobe signal due to variation in the level of the power supply voltage and adjusts a delay of the data signal using a result of the write training.
1. A memory device communicating with a system-on-chip (SoC), the memory device comprising:
a memory cell array;
a clock path that generates a clock signal by delaying a data strobe signal based on a variation in a level of a power supply voltage; and
a data latch that latches a data signal based on the clock signal, for writing the latched data signal to the memory cell array, the latched data signal indicating a magnitude of a delay that is used by the SoC for a write training.
2. The memory device of claim 1 , wherein the write training includes:
a first training mode that aligns the data strobe signal and the data signal based on a first level of the power supply voltage; and
a second training mode that aligns the data strobe signal and the data signal based on a second level of the power supply voltage, which is lower than the first level of the power supply voltage.
3. The memory device of claim 2 , wherein the magnitude of the delay is a difference between a first delay value provided as a result of the first training mode and a second delay value provided as a result of the second training mode.
4. The memory device of claim 2 , wherein:
the clock path is further configured to generate a first clock signal by delaying the data strobe signal based on the first level of the power supply voltage during the first training mode and generate a second clock signal by delaying the data strobe signal based on the second level of the power supply voltage during the second training mode,
the data latch is further configured to latch the data signal based on the first clock signal and write the latched data signal to the memory cell array during the first training mode and latch the data signal based on the second clock signal and write the latched data signal to the memory cell array during the second training mode,
the variation in the level of the power supply voltage indicates a voltage level difference between the first level and the second level, and
the magnitude of the delay data is a difference between a first delay value provided as a result of the first training mode and a second delay value provided as a result of the second training mode.
5. The memory device of claim 2 , wherein a voltage level difference between the first level and the second level corresponds to “tDQS2DQ_volt” of a low power double data rate (LPDDR).
6. The memory device of claim 1 , wherein the memory device is a Dynamic Random Access Memory (DRAM) operating in accordance with a LPDDR standard.
7. An electronic device comprising:
a memory device that communicates with a system-on-chip (SoC);
the SoC that generates a data strobe signal and a data signal; and
a power management integrated circuit (PMIC) that provides a first power supply voltage and a second power supply voltage to the memory device under control of the SoC, wherein:
the memory device comprises:
a memory cell array;
a clock path that generates a clock signal by delaying the data strobe signal based on a variation in a level of the second power supply voltage; and
a data latch that latches the data signal based on the clock signal, for writing latched data signal to the memory cell array, the latched data signal indicating a magnitude of a delay that is used by the SoC for a write training.
8. The electronic device of claim 7 , wherein the PMIC includes:
a control logic circuit that controls a first regulator and a second regulator under control of the SoC;
the first regulator that provides the first power supply voltage to the memory cell array; and
the second regulator that varies the second power supply voltage to the clock path.
9. The electronic device of claim 8 , wherein the second regulator is further configured to generate a first level of the second power supply voltage and a second level of the second power supply voltage which is lower than the first level of the second power supply voltage.
10. The electronic device of claim 7 , wherein the write training includes:
a first training mode that aligns the data strobe signal and the data signal based on a first level of the second power supply voltage; and
a second training mode that aligns the data strobe signal and the data signal based on a second level of the second power supply voltage which is lower than the first level of the second power supply voltage.
11. The electronic device of claim 10 , wherein the magnitude of the delay is a difference between a first delay value of the data signal provided as a result of the first training mode and a second delay value provided as a result of the second training mode.
12. The electronic device of claim 7 , wherein the SoC adjusts a setup margin of the data signal using the magnitude of the delay.
13. The electronic device of claim 7 , wherein the SoC includes a training module storing code that, when executed, performs the write training during a booting operation.
14. The electronic device of claim 7 , wherein the SoC decreases a setup margin of the data signal by a magnitude corresponding to half of the magnitude of the delay.
15. An electronic device comprising:
a memory module that communicates with a host and includes a plurality of memory devices; and
the host provides a data strobe signal, a data signal, and a power supply voltage, wherein:
a first memory device of the plurality of memory devices comprises:
a memory cell array;
a clock path that generates a clock signal by delaying the data strobe signal based on a variation in a level of the power supply voltage; and
a data latch that latches the data signal based on the clock signal, for writing the latched data signal to the memory cell array, the latched data signal indicating a magnitude of a delay that is used by the host for a write training.
16. The electronic device of claim 15 , wherein the plurality of memory devices includes second to eighth memory devices and each of the second to eighth memory devices has a similar structure to the first memory device.
17. The electronic device of claim 15 , wherein the memory module is further configured to include a serial component recognition device (SPD) storing product information of the memory module.
18. The electronic device of claim 15 , wherein the write training includes:
a first training mode that aligns the data strobe signal and the data signal based on a first level of the power supply voltage; and
a second training mode that aligns the data strobe signal and the data signal based on a second level of the power supply voltage which is lower than the first level of the power supply voltage.
19. The electronic device of claim 18 , wherein the magnitude of the delay is a difference between a first delay value provided as a result of the first training mode and a second delay value provided as a result of the second training mode.
20. The electronic device of claim 15 , wherein the SoC decreases a setup margin of the data signal by a magnitude corresponding to half of the magnitude of the delay.