IP Library › Granted Patent US 11,646,377
Granted Patent B2
US 11,646,377 · App. 17/223,600 · Granted May 9, 2023

Semiconductor device and method of manufacture

Inventors: Wei-Ting Chien (Hsinchu, TW); Su-Hao Liu (Jhongpu Township, TW); Liang-Yin Chen (Hsinchu, TW); Huicheng Chang (Tainan, TW); Yee-Chia Yeo (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
H01L29/7856H01L21/823418H01L29/41791H01L29/66545H01L29/66803H01L29/66818
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Quick Facts
Patent No.
US 11,646,377
App. No.
17/223,600
Granted
May 9, 2023
Kind
B2
Abstract

In accordance with some embodiments, a source/drain contact is formed by exposing a source/drain region through a first dielectric layer and a second dielectric layer. The second dielectric layer is recessed under the first dielectric layer, and a silicide region is formed on the source/drain region, wherein the silicide region has an expanded width.

Claims (33)

1. A method of manufacturing a semiconductor device, the method comprising:

exposing a source/drain region through a first dielectric layer and a second dielectric layer, the source/drain region being located at least partially within a semiconductor fin;

implanting dopants into the second dielectric layer;

after the implanting the dopants, recessing the second dielectric layer beneath the first dielectric layer; and

forming a silicide region on the source/drain region, wherein after the forming the silicide region the silicide region is located between the source/drain region and the first dielectric layer in a direction perpendicular to semiconductor fin.

2. The method of claim 1 , wherein the recessing the second dielectric layer is performed using a wet etching process.

3. The method of claim 2 , wherein the wet etching process utilizes hydrofluoric acid.

4. The method of claim 1 , wherein the implanting the dopants into the second dielectric layer also implants the dopants into the first dielectric layer.

5. The method of claim 1 , wherein the implanting the dopants is performed as a tilted implant.

6. The method of claim 1 , wherein the implanting the dopants implants germanium.

7. The method of claim 1 , wherein the second dielectric layer has an extension protruding from a sidewall of the first dielectric layer.

8. A method of manufacturing a semiconductor device, the method comprising:

etching a first dielectric material to form a first opening;

etching a second dielectric material to extend the first opening through the second dielectric material, wherein the first opening has a first width through the first dielectric material and a second width less than the first width through the second dielectric material;

recessing the second dielectric material from a sidewall of the first dielectric material to form a recess;

forming a silicide within the recess and within the first opening; and

filling a remainder of the first opening with a conductive material.

9. The method of claim 8 , wherein the recessing the second dielectric material comprises implanting a first dopant into the second dielectric material.

10. The method of claim 9 , wherein the first dopant comprises germanium.

11. The method of claim 10 , wherein the recessing the second dielectric material further comprises applying a wet etchant to the second dielectric material after the implanting the first dopant.

12. The method of claim 11 , wherein the wet etchant comprises hydrofluoric acid.

13. The method of claim 9 , wherein the implanting the first dopant also implants the first dopant into the first dielectric material.

14. The method of claim 9 , wherein the implanting the first dopant is performed as a tilted implant.

15. A semiconductor device comprising:

a source/drain region located within a semiconductor fin;

a first dielectric material over the semiconductor fin;

a contact etch stop layer located between the first dielectric material and the semiconductor fin; and

a conductive contact extending through the first dielectric material to make physical contact with a silicide region over the source/drain region, wherein the silicide region has a first width and the conductive contact has a second width adjacent to the silicide region less than the first width, wherein the first dielectric material has a first implantation region located along a sidewall of the first dielectric material adjacent to the conductive contact.

16. The semiconductor device of claim 15 , wherein the contact etch stop layer has a second implantation region located along a sidewall of the contact etch stop layer.

17. The semiconductor device of claim 16 , further comprising a third implantation region located within the source/drain region, the third implantation region, the second implantation region, and the first implantation region comprise the same dopant.

18. The semiconductor device of claim 15 , wherein the silicide region extends beneath the first dielectric material a distance of between about 0.5 nm and about 3 nm.

19. The semiconductor device of claim 15 , wherein the second width is between about 20 nm and about 45 nm.

20. The semiconductor device of claim 15 , wherein the first implantation region comprises boron.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 17, 2021
From: CHIEN, WEI-TING; LIU, SU-HAO; CHEN, LIANG-YIN; CHANG, HUICHENG; YEO, YEE-CHIA
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 056572/0399 →
Continuity (2)
Provisional Application 63068474 · Aug 21, 2020
Related Publication 20220059700A1 · Feb 24, 2022
Cited By (1)
US 12,557,620