Enabling stateless accelerator designs shared across mutually-distrustful tenants

1. An apparatus comprising:

a fully-homomorphic encryption (FHE)-capable circuitry to:

establish a secure session with a trusted environment executing on a host device communicably coupled to the apparatus;

generate, as part of establishing the secure session, per-tenant FHE keys for each tenant utilizing the FHE-capable circuitry, the per-tenant FHE keys utilized to encrypt tenant data provided to an FHE-capable compute kernel of the FHE-capable circuitry;

process tenant data that is in an FHE-encrypted format encrypted with a per-tenant FHE key of the per-tenant FHE keys; and

store the tenant data that is in the FHE-encrypted format encrypted with the per-tenant FHE key of the per-tenant FHE keys;

wherein an orchestrator component that is communicably coupled to the FHE-capable circuitry facilitates establishing the secure session with the trusted environment on the host device.

2. The apparatus of claim 1 , wherein the FHE-capable circuitry comprises at least one of the FHE-capable compute kernel comprising a partial configuration bitstream of a field-programmable gate array (FPGA) or an FHE-capable neural network.

3. The apparatus of claim 1 , wherein the FHE-capable circuitry to process the tenant data that is in the FHE-encrypted format comprising at least one of ciphertext or opaque data.

4. The apparatus of claim 1 , wherein the secure session is established using at least one of Diffie Hellman specification or a Security Protocol and Data Model (SPDM) specification.

5. The apparatus of claim 1 , wherein the trusted environment comprises a trusted execution environment (TEE) of the host device.

6. The apparatus of claim 1 , wherein the FHE-capable circuitry to process the tenant data and to process other tenant data encrypted with other per-tenant FHE keys in at least one of a time-sliced or temporal multi-tenant usage model.

7. The apparatus of claim 1 , wherein the apparatus comprises a hardware accelerator device comprising at least one a graphic processing unit (GPU), a central processing unit (CPU), or a programmable integrated circuit (IC).

8. The apparatus of claim 7 , wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic devices (CPLD).

9. A method comprising:

establishing, by a fully-homomorphic encryption (FHE)-capable circuitry of an accelerator device, a secure session with a trusted environment executing on a host device communicably coupled to the accelerator device;

generating, by the FHE-capable circuitry as part of establishing the secure session, per-tenant FHE keys for each tenant utilizing the FHE-capable circuitry, the per-tenant FHE keys utilized to encrypt tenant data provided to an FHE-capable compute kernel of the FHE-capable circuitry;

processing, by the FHE-capable circuitry, tenant data that is in an FHE-encrypted format encrypted with a per-tenant FHE key of the per-tenant FHE keys; and

storing, by the FHE-capable circuitry, the tenant data that is in the FHE-encrypted format encrypted with the per-tenant FHE key of the per-tenant FHE keys;

wherein an orchestrator component that is communicably coupled to the FHE-capable circuitry facilitates establishing the secure session with the trusted environment on the host device.

10. The method of claim 9 , wherein the FHE-capable circuitry comprises at least one of the FHE-capable compute kernel comprising a partial configuration bitstream of a field-programmable gate array (FPGA) or an FHE-capable neural network.

11. The method of claim 9 , wherein the FHE-capable circuitry to process the tenant data that is in the FHE-encrypted format comprising at least one of ciphertext or opaque data.

12. The method of claim 9 , wherein the FHE-capable circuitry to process the tenant data and to process other tenant data encrypted with other per-tenant FHE keys in at least one of a time-sliced or temporal multi-tenant usage model.

13. The method of claim 9 , wherein the accelerator device comprising at least one a graphic processing unit (GPU), a central processing unit (CPU), or a programmable integrated circuit (IC), and wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic devices (CPLD).

14. The method of claim 9 , wherein the trusted environment comprises a trusted execution environment (TEE) of the host device.

15. A non-transitory machine readable storage medium comprising instructions that, when executed, cause at least one processor to at least:

establish, by a fully-homomorphic encryption (FHE)-capable circuitry of an accelerator device comprising the at least one processor, a secure session with a trusted environment executing on a host device communicably coupled to the accelerator device;

generate, by the FHE-capable circuitry as part of establishing the secure session, per-tenant FHE keys for each tenant utilizing the FHE-capable circuitry, the per-tenant FHE keys utilized to encrypt tenant data provided to an FHE-capable compute kernel of the FHE-capable circuitry;

process, by the FHE-capable circuitry, tenant data that is in an FHE-encrypted format encrypted with a per-tenant FHE key of the per-tenant FHE keys; and

store, by the FHE-capable circuitry, the tenant data that is in the FHE-encrypted format encrypted with the per-tenant FHE key of the per-tenant FHE keys;

wherein an orchestrator component that is communicably coupled to the FHE-capable circuitry facilitates establishing the secure session with the trusted environment on the host device.

16. The non-transitory machine readable storage medium of claim 15 , wherein the FHE-capable circuitry comprises at least one of the FHE-capable compute kernel comprising a partial configuration bitstream of a field-programmable gate array (FPGA) or an FHE-capable neural network.

17. The non-transitory machine readable storage medium of claim 15 , wherein the FHE-capable circuitry to process the tenant data that is in the FHE-encrypted format comprising at least one of ciphertext or opaque data.

18. The non-transitory machine readable storage medium of claim 15 , wherein the FHE-capable circuitry to process the tenant data and to process other tenant data encrypted with other per-tenant FHE keys in at least one of a time-sliced or temporal multi-tenant usage model.

19. The non-transitory machine readable storage medium of claim 15 , wherein the trusted environment comprises a trusted execution environment (TEE) of the host device.

20. The non-transitory machine readable storage medium of claim 15 , wherein the secure session is established using at least one of Diffie Hellman specification or a Security Protocol and Data Model (SPDM) specification.