Integrated circuit structure with backside via

1. A method comprising:

forming a transistor over a substrate, the transistor comprising a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure;

removing at least a portion of the substrate to expose a backside of the transistor;

forming a backside dielectric layer over the exposed backside of the transistor;

forming a backside via opening in the backside dielectric layer to expose a backside of the first source/drain epitaxial structure of the transistor;

forming an epitaxial regrowth layer over the exposed backside of the first source/drain epitaxial structure of the transistor; and

forming a backside via in the backside via opening and over the epitaxial regrowth layer.

2. The method of claim 1 , further comprising:

forming a via spacer lining sidewalls of the backside via opening before forming the epitaxial regrowth layer.

3. The method of claim 1 , further comprising:

forming a via spacer lining sidewalls of the backside via opening after forming the epitaxial regrowth layer and before forming the backside via.

4. The method of claim 1 , further comprising:

forming a via spacer lining sidewalls of the backside via opening; and

after forming the via spacer, forming a silicide region in the epitaxial regrowth layer.

5. The method of claim 4 , wherein forming the via spacer is performed prior to forming the epitaxial regrowth layer.

6. The method of claim 4 , wherein forming the via spacer is performed after forming the epitaxial regrowth layer and prior to forming the silicide region.

7. The method of claim 1 , wherein forming the epitaxial regrowth layer comprises doping the epitaxial regrowth layer with n-type or p-type dopants.

8. A method comprising:

forming a first recess and a second recess in a first side of a substrate;

forming a sacrificial layer on a bottom surface of the first recess;

forming a first epitaxial region over the sacrificial layer in the first recess and a second epitaxial region in the second recess;

removing at least a portion of the substrate to expose the sacrificial layer;

forming a backside dielectric layer along sidewalls of the sacrificial layer;

removing the sacrificial layer to form a third recess in the backside dielectric layer;

forming a third epitaxial region on the first epitaxial region in the third recess; and

forming a backside via to the third epitaxial region in the third recess.

9. The method of claim 8 , wherein the first recess is deeper than the second recess.

10. The method of claim 8 , wherein removing the substrate exposes the second epitaxial region.

11. The method of claim 8 , wherein the substrate comprises a fin, wherein the first recess and the second recess are formed in the fin, further comprising:

forming isolation regions on opposing sides of the fin, wherein the isolation regions extends along opposite sidewalls of the second epitaxial region.

12. The method of claim 8 , further comprising:

forming spacers on sidewalls of the third recess prior to forming the third epitaxial region.

13. The method of claim 12 , wherein the spacers completely encircles the backside via in a plan view.

14. The method of claim 8 , further comprising:

after forming the third epitaxial region, forming spacers along sidewalls of the third recess over the third epitaxial region.

15. A method comprising:

forming a fin protruding from a first side of a substrate;

forming isolation region over the substrate on opposing sides of the fin, wherein the fin protrudes above the isolation region;

performing a first etch process to form a first recess and a second recess in the fin, wherein the first recess and the second recess extends below an upper surface of the isolation region;

epitaxially growing a sacrificial layer on a bottom surface of the first recess;

epitaxially growing a first epitaxial region over the sacrificial layer in the first recess, wherein the first epitaxial region is a different material than the sacrificial layer;

epitaxially growing a second epitaxial region in the second recess;

removing at least a portion of a second side of the substrate to expose the sacrificial layer, the second epitaxial region, and a bottom side of the isolation region;

forming a backside dielectric layer on the second epitaxial region, along sidewalls of the sacrificial layer, and the bottom side of the isolation region;

removing the sacrificial layer to form a third recess in the backside dielectric layer, wherein the first epitaxial region is exposed in the third recess;

forming a regrowth layer on the first epitaxial region in the third recess; and

forming a backside via to the regrowth layer in the third recess.

16. The method of claim 15 , further comprising, prior to epitaxially growing the sacrificial layer, performing a second etch process to extend a depth of the first recess, wherein after performing the second etch process the depth of the first recess is greater than a depth of the second recess.

17. The method of claim 15 , further comprising:

forming spacers along sidewalls of the third recess prior to forming the regrowth layer.

18. The method of claim 15 , further comprising:

forming spacers along sidewalls of the third recess after forming the regrowth layer.

19. The method of claim 15 , wherein the sacrificial layer is free of n-type and p-type dopants.

20. The method of claim 15 , further comprising:

siliciding a surface of the regrowth layer prior to forming the backside via.