Lateral diffusion metal oxide semiconductor device and method for fabricating the same
A method for fabricating a lateral diffusion metal oxide semiconductor (LDMOS) device includes the steps of first forming a first fin-shaped structure and a second fin-shaped structure on a substrate, forming a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, forming a first gate structure on the first fin-shaped structure and a second gate structure on the second fin-shaped structure, forming a source region on the first fin-shaped structure, forming a drain region on the second fin-shaped structure, and forming a contact field plate directly on the STI.
1. A method for fabricating a lateral diffusion metal oxide semiconductor (LDMOS) device, comprising:
forming a first fin-shaped structure on a substrate;
forming a shallow trench isolation (STI) adjacent to the first fin-shaped structure, wherein a top surface of the STI is lower than a top surface of the substrate;
forming a first gate structure on the first fin-shaped structure; and
forming a contact field plate adjacent to the first gate structure and directly on and contacting the STI, wherein a top surface of the STI directly contacting a bottom surface of the contact field plate is even with a top surface of surrounding STI and lower than the top surface of the substrate.
2. The method of claim 1 , further comprising:
forming a second fin-shaped structure adjacent to the first fin-shaped structure, wherein the STI is between the first fin-shaped structure and the second fin-shaped structure;
forming a second gate structure on the second fin-shaped structure;
forming a source region adjacent to one side of the first gate structure on the first fin-shaped structure;
forming a drain region adjacent to one side of the second gate structure on the second fin-shaped structure;
forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure;
transforming the first gate structure and the second gate structure into a first metal gate and a second metal gate; and
forming a first contact plug on the source region and a second contact plug on the drain region.
3. The method of claim 2 , wherein the contact field plate is between the first gate structure and the second gate structure.
4. The method of claim 2 , wherein a width of the second gate structure is less than a width of the first gate structure.
5. The method of claim 2 , wherein the contact field plate and the first contact plug comprise same material.
6. The method of claim 2 , wherein a bottom surface of the contact field plate is lower than a bottom surface of the first contact plug.
7. The method of claim 2 , wherein top surfaces of the contact field plate and the first contact plug are coplanar.
8. A lateral diffusion metal oxide semiconductor (LDMOS) device, comprising:
a first fin-shaped structure on a substrate;
a shallow trench isolation (STI) adjacent to the first fin-shaped structure, wherein a top surface of the STI is lower than a top surface of the substrate;
a first gate structure on the first fin-shaped structure; and
a contact field plate adjacent to the first gate structure and directly on and contacting the STI, wherein a top surface of the STI directly contacting a bottom surface of the contact field plate is even with a top surface of surrounding STI and lower than the top surface of the substrate.
9. The semiconductor device of claim 8 , further comprising:
a second fin-shaped structure adjacent to the first fin-shaped structure, wherein the STI is between the first fin-shaped structure and the second fin-shaped structure;
a second gate structure on the second fin-shaped structure;
a source region adjacent to one side of the first gate structure on the first fin-shaped structure;
a drain region adjacent to one side of the second gate structure on the second fin-shaped structure;
an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; and
a first contact plug on the source region and a second contact plug on the drain region.
10. The semiconductor device of claim 9 , wherein the contact field plate is between the first gate structure and the second gate structure.
11. The semiconductor device of claim 9 , wherein a width of the second gate structure is less than a width of the first gate structure.
12. The semiconductor device of claim 9 , wherein the contact field plate and the first contact plug comprise same material.
13. The semiconductor device of claim 9 , wherein a bottom surface of the contact field plate is lower than a bottom surface of the first contact plug.
14. The semiconductor device of claim 9 , wherein top surfaces of the contact field plate and the first contact plug are coplanar.
15. A lateral diffusion metal oxide semiconductor (LDMOS) device, comprising:
a first fin-shaped structure on a substrate;
a shallow trench isolation (STI) adjacent to the first fin-shaped structure, wherein a top surface of the STI is lower than a top surface of the first fin-shaped structure;
a first gate structure on the first fin-shaped structure and the STI, wherein a bottom surface of the first gate structure directly contacting a top surface of the STI is lower than a bottom surface of the first gate structure on the first fin-shaped structure; and
a contact field plate adjacent to the first gate structure and directly on the STI.
16. The semiconductor device of claim 15 , further comprising:
a second fin-shaped structure adjacent to the first fin-shaped structure, wherein the STI is between the first fin-shaped structure and the second fin-shaped structure;
a second gate structure on the second fin-shaped structure;
a source region adjacent to one side of the first gate structure on the first fin-shaped structure;
a drain region adjacent to one side of the second gate structure on the second fin-shaped structure;
an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; and
a first contact plug on the source region and a second contact plug on the drain region.
17. The semiconductor device of claim 16 , wherein the contact field plate is between the first gate structure and the second gate structure.
18. The semiconductor device of claim 16 , wherein the contact field plate and the first contact plug comprise same material.
19. The semiconductor device of claim 16 , wherein a bottom surface of the contact field plate is lower than a bottom surface of the first contact plug.
20. The semiconductor device of claim 16 , wherein top surfaces of the contact field plate and the first contact plug are coplanar.