IP Library › Granted Patent US 11,653,119
Granted Patent B2
US 11,653,119 · App. 17/436,820 · Granted May 16, 2023

Solid-state image sensor and imaging device

Inventors: Sachio Akebono (Kanagawa, JP); Yosuke Ueno (Kanagawa, JP)
Assignee: Sony Semiconductor Solution Corporation
H04N5/3698H04N5/37455H04N5/37457
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Quick Facts
Patent No.
US 11,653,119
App. No.
17/436,820
Granted
May 16, 2023
Kind
B2
Abstract

In a solid-state image sensor provided with a comparator that compares a reference signal and a pixel signal, the image quality of image data is improved. A voltage divider circuit supplies a divided voltage of an input voltage and a predetermined reference voltage that are input. An input-side differential transistor outputs a drain current corresponding to the gate-source voltage between the divided voltage input to the gate and a predetermined source voltage. An output-side differential transistor outputs a voltage corresponding to the drain current as a result of comparison between the input voltage and the reference voltage. A control transistor reduces the gate-source voltage in a case where the input voltage is out of a predetermined range.

Claims (32)

1. A solid-state image sensor comprising:

a voltage divider circuit that supplies a divided voltage of an input voltage and a predetermined reference voltage that are input;

an input-side differential transistor that outputs a drain current corresponding to a gate-source voltage between the divided voltage input to the gate and a predetermined source voltage;

an output-side differential transistor that outputs a voltage corresponding to the drain current as a result of comparison between the input voltage and the reference voltage; and

a control transistor chat reduces the gate-source voltage in a case where the input voltage is out of a predetermined range.

2. The solid-state image sensor according to claim 1 further comprising:

a tail current source commonly connected to the source of the input-side differential transistor and the source of the output-side differential transistor;

an input-side current mirror transistor having the drain and gate connected to the drain of the input-side differential transistor; and

an output-side current mirror transistor having the drain connected to the drain of the output-side differential transistor, and the gate connected to the gate of the input-side current mirror transistor, wherein

the control transistor has the gate connected to the output node of the voltage divider circuit, and the source connected to a connection point of the input-side differential transistor and the input-side current mirror transistor.

3. The solid-state image sensor according to claim 1 further comprising:

a tail current source commonly connected to the source of the input-side differential transistor and the source of the output-side differential transistor;

an input-side resistor having one end connected to the drain of the input-side differential transistor; and

an output-side resistor having one end connected to the drain of the output-side differential transistor, wherein

the control transistor has the gate connected to the output node of the voltage divider circuit, and the source connected to a connection point of the input-side differential transistor and the input-side resistor.

4. The solid-state image sensor according to claim 3 further comprising:

an input-side current mirror transistor having the gate connected to a connection point of the input-side differential transistor and the input-side resistor, and the drain connected to another end of the input-side resistor; and

an output-side current mirror transistor having the drain connected to another end of the output-side resistor, and the gate connected to the gate of the input-side current mirror transistor.

5. The solid-state image sensor according to claim 1 , wherein

the input-side differential transistor, the output-side differential transistor, and the control transistor are P-type transistors, and

the control transistor reduces a drain voltage of the input-side differential transistor in a case where the input voltage is lower than a predetermined value.

6. The solid-state image sensor according to claim 1 , wherein

the input-side differential transistor, the output-side differential transistor, and the control transistor are N-type transistors, and

the control transistor increases a drain voltage of the input-side differential transistor in a case where the input voltage is higher than a predetermined value.

7. The solid-state image sensor according to claim 1 , wherein

the voltage divider circuit changes a voltage division ratio between the input voltage and the reference voltage according to a control signal.

8. An imaging device comprising:

a voltage divider circuit that supplies a divided voltage of an input voltage and a predetermined reference voltage that are input;

an input-side differential transistor that outputs a drain current corresponding to a gate-source voltage between the divided voltage input to the gate and a predetermined source voltage;

an output-side differential transistor that outputs a voltage corresponding to the drain, current as a result of comparison between the input voltage and the reference voltage;

a control transistor that reduces the gate-source voltage in a case where toe input voltage is out of a predetermined range; and

a counter that counts a count value on a basis of the comparison result.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2021
From: AKEBONO, SACHIO; UENO, YOSUKE
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 057400/0356 →
Priority Claims (1)
JP JP2019-046578 · Mar 14, 2019 · national
Continuity (1)
Related Publication 20220174231A1 · Jun 2, 2022