Solid-state image capturing element with floating diffusion layers processing a signal undergoing pixel addition

1. A solid-state image capturing element comprising:

a pair of first floating diffusion layers arranged in a direction perpendicular to a predetermined direction;

a pair of second floating diffusion layers arranged in the perpendicular direction and adjacent to the pair of first floating diffusion layers in the predetermined direction;

a first connection circuit configured to select at least one of the pair of first floating diffusion layers and to connect the selected first floating diffusion layer to a predetermined first wire;

a second connection circuit configured to select at least one of the pair of second floating diffusion layers and to connect the selected second floating diffusion layer to the first wire; and

an output circuit configured to output a signal according to an amount of charge of at least one of the pair of first floating diffusion layers or the pair of second floating diffusion layers,

wherein the first connection circuit includes:

a first connection transistor configured to connect one of the pair of first floating diffusion layers to a second wire connected to the first wire according to a first control signal;

a second connection transistor configured to connect another one of the pair of first floating diffusion layers to a third wire according to a second control signal; and

a third connection transistor configured to connect the first wire to the third wire according to a third control signal, and

the second connection circuit includes a fourth connection transistor that connects one of the pair of second floating diffusion layers to the second wire according to a fourth control signal.

2. The solid-state image capturing element according to claim 1 , wherein

a reset transistor is disposed between the first connection transistor and the third connection transistor in the predetermined direction, and

a selection transistor is disposed between the first connection transistor and the second connection transistor in the perpendicular direction.

3. The solid-state image capturing element according to claim 1 , wherein

the first connection transistor and the third connection transistor are disposed adjacent to each other in the predetermined direction, and

a selection transistor is disposed between the first connection transistor and the second connection transistor in the perpendicular direction.

4. The solid-state image capturing element according to claim 1 , wherein

a reset transistor is disposed between the first connection transistor and the third connection transistor in the predetermined direction, and

the first connection transistor and the second connection transistor are disposed adjacent to each other in the perpendicular direction.

5. The solid-state image capturing element according to claim 1 , wherein

the first connection transistor and the third connection transistor are disposed adjacent to each other in the predetermined direction, and

the first connection transistor and the second connection transistor are disposed adjacent to each other in the perpendicular direction.

6. The solid-state image capturing element according to claim 1 , wherein

the second connection circuit further includes:

a fifth connection transistor configured to connect one of the pair of second floating diffusion layers to a predetermined second wire according to a fifth control signal; and

a sixth connection transistor configured to connect another one of the pair of second floating diffusion layers to a predetermined third wire according to a sixth control signal.

7. The solid-state image capturing element according to claim 6 , wherein

a reset transistor is disposed adjacent to the fifth connection transistor in the predetermined direction.

8. The solid-state image capturing element according to claim 6 , wherein

a predetermined number of the fifth connection transistors are arranged adjacent to each other in the predetermined direction.

9. The solid-state image capturing element according to claim 6 , wherein

the output circuit further includes:

a first reset transistor configured to connect a predetermined power node to the first wire according to a first reset signal; and

a second reset transistor configured to connect a predetermined power node to the first wire according to a second reset signal.

10. The solid-state image capturing element according to claim 1 , further comprising:

a pair of third floating diffusion layers arranged in the perpendicular direction;

a pair of fourth floating diffusion layers arranged in the perpendicular direction and adjacent to the pair of third floating diffusion layers in the predetermined direction;

a third connection circuit configured to select at least one of the pair of third floating diffusion layers and to connect the selected third floating diffusion layer to the first wire; and

a fourth connection circuit configured to select at least one of the pair of fourth floating diffusion layers and to connect the selected fourth floating diffusion layer to the first wire.

11. The solid-state image capturing element according to claim 1 , further comprising:

a signal processing unit configured to perform processing of measuring a distance according to a time of flight of light on a basis of the output signal.

12. The solid-state image capturing element according to claim 11 , further comprising:

a pair of third floating diffusion layers arranged in the perpendicular direction;

a pair of fourth floating diffusion layers arranged in the perpendicular direction;

a third connection circuit configured to select at least one of the pair of third floating diffusion layers and to connect the selected third floating diffusion layer to a predetermined second wire; and

a fourth connection circuit configured to select at least one of the pair of fourth floating diffusion layers and to connect the selected fourth floating diffusion layer to the second wire,

wherein the output circuit outputs the signal according to an amount of charge of at least one of the pair of first floating diffusion layers or the pair of second floating diffusion layers, and a signal according to an amount of charge of at least one of the pair of third floating diffusion layers or the pair of fourth floating diffusion layers.

13. The solid-state image capturing element according to claim 11 , further comprising:

a pair of third floating diffusion layers arranged in the perpendicular direction;

a pair of fourth floating diffusion layers arranged in the perpendicular direction;

a third connection circuit configured to select at least one of the pair of third floating diffusion layers and to connect the selected third floating diffusion layer to the first wire; and

a fourth connection circuit configured to select at least one of the pair of fourth floating diffusion layers and to connect the selected fourth floating diffusion layer to the first wire,

wherein the output circuit outputs the signal according to an amount of charge of at least one of the pair of first floating diffusion layers or the pair of second floating diffusion layers, and a signal according to an amount of charge of at least one of the pair of third floating diffusion layers or the pair of fourth floating diffusion layers.

14. The solid-state image capturing element according to claim 11 , further comprising:

a first transfer transistor configured to transfer a charge from a first photoelectric conversion element to one of the pair of first floating diffusion layers;

a second transfer transistor configured to transfer a charge from the first photoelectric conversion element to another one of the pair of first floating diffusion layers;

a third transfer transistor configured to transfer a charge from a second photoelectric conversion element to one of the pair of second floating diffusion layers; and

a fourth transfer transistor configured to transfer a charge from the second photoelectric conversion element to another one of the pair of second floating diffusion layers.

15. An electronic device comprising:

a pair of first floating diffusion layers arranged in a direction perpendicular to a predetermined direction;

a pair of second floating diffusion layers arranged in the perpendicular direction and adjacent to the pair of first floating diffusion layers in the predetermined direction;

a first connection circuit configured to select at least one of the pair of first floating diffusion layers and to connect the selected first floating diffusion layer to a predetermined first wire;

a second connection circuit configured to select at least one of the pair of second floating diffusion layers and to connect the selected second floating diffusion layer to the first wire;

an output circuit configured to output a signal according to an amount of charge of at least one of the pair of first floating diffusion layers or the pair of second floating diffusion layers; and

an analog-to-digital conversion unit configured to perform analog-to-digital conversion processing on the signal,

wherein the first connection circuit includes:

a first connection transistor configured to connect one of the pair of first floating diffusion layers to a second wire connected to the first wire according to a first control signal;

a second connection transistor configured to connect another one of the pair of first floating diffusion layers to a third wire according to a second control signal; and

a third connection transistor configured to connect the first wire to the third wire according to a third control signal, and

the second connection circuit includes a fourth connection transistor that connects one of the pair of second floating diffusion layers to the second wire according to a fourth control signal.