Layered super-reticle computing : architectures and methods
Embodiments herein may present an integrated circuit or a computing system having an integrated circuit, where the integrated circuit includes a physical network layer, a physical computing layer, and a physical memory layer, each having a set of dies, and a die including multiple tiles. The physical network layer further includes one or more signal pathways dynamically configurable between multiple pre-defined interconnect topologies for the multiple tiles, where each topology of the multiple pre-defined interconnect topologies corresponds to a communication pattern related to a workload. At least a tile in the physical computing layer is further arranged to move data to another tile in the physical computing layer or a storage cell of the physical memory layer through the one or more signal pathways in the physical network layer. Other embodiments may be described and/or claimed.
1. A package, comprising:
a network layer with a first side and a second side opposite the first side, wherein the network layer includes one or more tiles having a first side and a second side opposite the first side, wherein at least a portion of the one or more tiles in the network layer are communicatively coupled;
one or more dies coupled with the first side of the network layer and electrically coupled with the first side of at least one of the one or more tiles in the network layer;
wherein the second side of at least one of the one or more tiles in the network layer are directly electrically coupled with at least one of a plurality of connectors at the second side of the network layer;
wherein the one or more tiles of the network layer form a multi-hop packet switched network; and
wherein at least one of the one or more dies are directly electrically coupled with at least one of the plurality of connectors at the second side of the network layer.
2. The package of claim 1 , wherein the one or more dies are one or more compute dies.
3. The package of claim 1 , wherein one of the one or more dies includes one or more tiles.
4. The package of claim 1 , wherein the multi-hop packet switched network is to move data between the one or more dies.
5. The package of claim 1 , wherein the multi-hop packet switched network is to move data between the one or more dies and a memory layer coupled with the plurality of connectors at the second side of the network layer.
6. The package of claim 1 , wherein the multi-hop packet switched network is configurable via software.
7. The package of claim 1 , wherein the one or more tiles in the network layer are physically separated.
8. The package of claim 1 , wherein at least one of the one or more tiles of the network layer are directly electrically coupled with another of the one or more tiles of the network layer.
9. The package of claim 1 , wherein the one or more tiles of the network layer form a super-reticle.
10. The package of claim 1 , wherein the one or more dies form a super-reticle.
11. The package of claim 1 , further comprising a substrate electrically coupled with the plurality of connectors.
12. A system, comprising:
a package, including:
a network layer with a first side and a second side opposite the first side, wherein the network layer includes one or more tiles having a first side and a second side opposite the first side, and wherein the one or more tiles of the network layer form a multi-hop packet switched network;
one or more dies coupled with the first side of the network layer and electrically coupled with the first side of at least one of the one or more tiles in the network layer;
wherein the second side of the one or more tiles in the network layer are directly electrically coupled with at least one of a plurality of connectors at the second side of the network layer;
wherein at least one of the one or more dies are directly electrically coupled with at least one of the plurality of connectors at the second side of the network layer; and
a memory layer with a first side at a second side opposite the first side, the first side of the memory layer electrically coupled with the plurality of connectors at the second side of the network layer of the package.
13. The system of claim 12 , wherein the one or more dies, the network layer, or the memory layer forms a super-reticle.
14. The system of claim 12 , wherein the memory layer includes a plurality of dies or a plurality of storage cells.
15. The system of claim 12 , wherein the multi-hop packet switched network is to move data between the one or more dies and the memory layer.
16. The system of claim 12 , wherein the multi-hop packet switched network is configurable via software.
17. The system of claim 12 , wherein the multi-hop packet switched network is configurable to electrically couple one of the one or more dies with a storage cell in the memory layer.
18. The system of claim 12 , wherein at least one of the one or more tiles in the network layer are electrically coupled with another of the one or more tiles in the network layer.
19. The system of claim 12 , further including:
a printed circuit board, PCB, with a first side and a second side opposite the first side; and
wherein the second side of the memory layer is electrically coupled with the first side of the PCB.