Managing open blocks in memory systems
Systems, methods, and apparatus including computer-readable mediums for managing open blocks in memory systems such as NAND flash memory devices are provided. In one aspect, a method includes: evaluating a read disturbance level of an open block in a memory, the open block having one or more programmed word lines and one or more blank word lines, and in response to determining that the read disturbance level of the open block is beyond a threshold level, managing each memory cell in at least one of the blank word lines to have a smaller data storing capacity than each memory cell in at least one of the one or more programmed word lines so as to reduce impact of read disturbance.
1. A method of managing open blocks in a memory, the method comprising:
evaluating a read disturbance level of an open block in the memory, the open block comprising one or more programmed pages associated with one or more programmed word lines and one or more blank pages associated with one or more blank word lines; and
in response to determining that the read disturbance level of the open block is beyond a threshold level, managing memory cells in at least one of the one or more blank word lines in the open block for data storage such that each memory cell in the at least one of the one or more blank word lines in the open block has a smaller data storing capacity than each memory cell in at least one of the one or more programmed word lines in the open block.
2. The method of claim 1 , wherein each memory cell in the at least one of the one or more programmed word lines has a first storing level for storing a first number of bits, and
wherein managing memory cells in at least one of the one or more blank word lines in the open block comprises:
degrading each memory cell in the at least one of the one or more blank word lines to have a second storing level for storing a second number of bits, the second number being smaller than the first number.
3. The method of claim 2 , wherein the first number of bits represents a first number of states, and the second number of bits represents a second number of states, the second number of states being smaller than the first number of states, and
wherein managing memory cells in at least one of the one or more blank word lines in the open block comprises:
degrading the memory cells in the at least one of the one or more blank word lines by configuring threshold voltage ranges of the memory cells in the at least one of the one or more blank word lines to represent the second number of states.
4. The method of claim 1 , wherein each memory cell in the at least one of the one or more programmed word lines is capable of representing a first number of states, and
wherein managing memory cells in at least one of the one or more blank word lines in the open block comprises at least one of:
degrading each memory cell in the at least one of the one or more blank word lines to be capable of representing a second number of states, the second number being smaller than the first number, or
degrading the memory cells in the at least one of the one or more blank word lines by reconfiguring threshold voltage ranges of the second number of states representable by the memory cells in the at least one of the one or more blank word lines.
5. The method of claim 4 , wherein managing memory cells in at least one of the one or more blank word lines in the open block comprises:
degrading each memory cell in at least two adjacent blank word lines of the one or more blank word lines to be capable of representing the second number of states; and
combining at least two memory cells in the at least two adjacent blank word lines to represent a third number of states, each of the at least two memory cells being in a respective one of the at least two adjacent blank word lines, the third number of states being a combination of the second number of states of each of the at least two memory cells.
6. The method of claim 1 , wherein each memory cell in the at least one of the one or more programmed word lines is capable of representing a series of states, and
wherein the method comprises:
storing data into the memory cells in the at least one of the one or more blank word lines by representing the data by the memory cells in at least two selected states among the series of states, each of the at least two selected states having a threshold voltage higher than other unselected states among the series of states.
7. The method of claim 6 , wherein the memory cells in the at least one of the one or more blank word lines are programmable into a lower page and at least one higher page and
wherein storing data into the memory cells in the at least one of the one or more blank word lines comprises:
programming bits in the lower page to be a fixed pattern; and
programming bits in the at least one higher page to represent the data.
8. The method of claim 1 , wherein each memory cell in the at least one of the one or more programmed word lines is capable of representing a plurality of states including an erased state and a series of programmed states, each of the plurality of states having a respective threshold voltage range,
wherein the method comprises:
determining that a memory cell in the open block has overlapping states at least by determining that the erased state of the memory cell has a higher limit voltage in a corresponding threshold voltage range of at least one of the series of programmed states, and
wherein determining that the read disturbance level of the open block is beyond a threshold level comprises:
determining that a number of memory cells having overlapping states in one of the one or more blank word lines exceeds a threshold number.
9. The method of claim 1 , wherein determining that the read disturbance level of the open block is beyond a threshold level comprises:
determining that a number of error bits in one of the one or more programmed pages exceeds a threshold number.
10. The method of claim 9 , wherein the threshold number is predetermined based on a number of correction bits in error correction codes (ECCs) for the one of the one or more programmed pages.
11. The method of claim 9 , wherein the one of the one or more programmed pages is associated with a specific word line in the open block, memory cells in the specific word line being more sensitive to be disturbed than memory cells in other word lines in the open block.
12. The method of claim 11 , wherein each bit in the one of the one or more programmed pages is programmed to be a fixed value.
13. The method of claim 11 , wherein the one of the one or more programmed pages comprises a series of sequential bits, and
wherein the method comprises:
programming at least one bit in at least one of a starting region or an ending region of the series of sequential bits to be a fixed value.
14. The method of claim 11 , wherein the one of the one or more programmed pages comprises multiple chunks each having a series of sequential bits, and
wherein the method comprises:
programming at least one bit in at least one of a starting region or an ending region of the series of sequential bits in each of the chunks to be a fixed value.
15. The method of claim 11 , wherein the one of the one or more programmed pages comprises a series of sequential bits, and
wherein the method comprises:
programming alternating bits in the series with data and a fixed value.
16. The method of claim 1 , wherein evaluating a read disturbance level of an open block in the memory comprises:
evaluating the read disturbance level based on at least one of characteristics of the open block, the characteristics of the open block comprising an erase count and a read count.
17. The method of claim 1 , wherein managing the memory cells in at least one of the one or more blank word lines comprises
managing the memory cells in at least one of the one or more blank word lines such that data is represented by non-overlapping states of the memory cells in the at least one of the one or more blank word lines.
18. The method of claim 1 , further comprising:
evaluating a read disturbance level of a second open block, the second open block comprising one or more programmed pages and one or more blank pages; and
in response to determining that the read disturbance level of the second open block is below the threshold level, storing data in at least one of the one or more blank pages with a same data storing capacity as at least one of the one or more programmed pages.
19. The method of claim 1 , further comprising:
evaluating a read disturbance level of a second open block, the second open block comprising one or more second programmed pages and one or more second blank pages; and
in response to determining that the read disturbance level of the second open block is beyond a second threshold level, migrating data stored in the one or more second programmed pages of the second open block then erasing the second open block after the migration, the second threshold level being higher than the threshold level,
wherein managing the memory cells in the one or more blank word lines in the open block is in response to determining that the read disturbance level of the open block is beyond the threshold level and below the second threshold level.
20. A method comprising:
managing memory cells in one or more blank word lines in an open block of a memory for data storage such that each memory cell in at least one of the one or more blank word lines in the open block has a smaller data storing capacity than each memory cell in at least one of one or more programmed word lines in the open block, then
storing data in the memory cells in the at least one of the one or more blank word lines in the open block.