Multi-phase topology synthesis of a network-on-chip (NoC)
A process is disclosed that automatically creates a network-on-chip (NoC) very quickly using a set of constraints, which are requirements for the NoC. The process takes a set of constraints as inputs and produces a NoC with all its elements configured and a placement of such elements on the floorplan of the chip.
1. A method for generation of a network, the method comprising:
receiving constraints for the network;
executing topology synthesis using the constraints to generate an abstract network as a solution for implementation of the network, wherein the abstract network includes abstract network elements representing simplified real elements;
generating, using the abstract network, a real network representation of the network, wherein the real network complies with the constraints for the network; and
producing an actual network, using the real network and elements from a network component library to optimize the real network based on location and pipelining in order to minimize logic congestion and to optimize timing, respectively, in the actual network.
2. The method of claim 1 , wherein the abstract network elements include at least one abstract switch, at least two abstract protocol converters, and at least one abstract adapter.
3. The method of claim 2 , wherein the abstract network elements are communicatively connected together through abstract links.
4. The method of claim 1 , wherein the step of generating includes receiving input of network element descriptions from a network element library.
5. The method of claim 4 , wherein network elements are selected based on their network element description to satisfy the constraints.
6. The method of claim 1 , wherein the constraints include a previously generated network.
7. The method of claim 1 , wherein the method is repeated with at least one constraint of the constraints is changed and the actual network, which was a previously generated, is included as an additional constraint.
8. A method for generation of a network, the method comprising:
receiving constraints for the network, the constraints include an abstract network representation for the network;
executing topology synthesis using the constraints to generate a second abstract network as a solution for implementation of the network, wherein the second abstract network includes abstract network elements;
generating, using the second abstract network, a real network representation of the network, wherein the real network complies with the constraints for the network;
producing an actual network using the real network and elements from a NoC component library.
9. The method of claim 8 further comprising optimizing the actual network based on location and pipelining of the elements in order to reduce congestion and to improve timing, respectively.
10. A non-transitory computer readable medium for storing code, which when executed by one or more processors, would cause the processor to:
execute topology synthesis using a plurality of constraints;
generate an abstract network-on-chip (NoC) as a solution for implementation of a physical NoC, wherein the abstract NoC includes abstract elements representing real elements;
generate, using the abstract NoC, a real NoC that complies with the constraints;
optimize the real network based on location and pipelining to produce an optimized NoC.