Memory device, controller controlling the same, memory system including the same, and operating method thereof

1. A controller configured to control a memory device, the controller comprising:

controller processing circuitry configured to

generate a clock and to output the clock to the memory device;

generate a command address signal to operate the memory device;

transmit the command address signal in response to the clock; and

transmit data to and receive data from the memory device through a data channel according to a transmission signaling mode selected from a first transmission signaling mode and a second transmission signaling mode,

wherein flag information, associated with at least one mode parameter, is received from the memory device during a training period of the memory device, and one of the first transmission signaling mode and the second transmission signaling mode is determined to be the transmission signaling mode using the flag information.

2. The controller of claim 1 , wherein the controller processing circuitry is further configured to make a training request for the data channel.

3. The controller of claim 1 , wherein the first transmission signaling mode is a non-return-to-zero (NRZ) mode, and

the second transmission signaling mode is a pulse amplitude modulation 4-level (PAM4) mode.

4. The controller of claim 1 , wherein the controller processing circuitry is further configured to:

generate a command address reference signal corresponding to the command address signal;

store the command address reference signal;

compare the stored command address reference signal with the command address reference signal received from the memory device; and

adjust a phase or timing of the command address signal based on a comparison result of the comparator.

5. The controller of claim 1 , wherein the transmission signaling mode varies, in real time, according to environment information of the data channel.

6. The controller of claim 1 , wherein the controller processing circuitry makes a training request for the data channel, and wherein the transmission signaling mode is detected by the memory device according to the training request.

7. The controller of claim 1 , wherein the controller is configured to communicate with the memory device according to the transmission signaling mode stored in a mode register.

8. The controller of claim 1 , wherein one bit of data, corresponding to each of a first voltage level and a second voltage level higher than the first voltage level, is transmitted through the data channel according to the first transmission signaling mode.

9. The controller of claim 1 , wherein two bits of data, corresponding to each of a first voltage level, a second voltage level higher than the first voltage level, a third voltage level higher than the second voltage level, and a fourth voltage level higher than the third voltage level, are transmitted through the data channel according to the second transmission signaling mode.

10. A method of operating a controller configured to control a memory device, the method comprising:

generating a clock and to output the clock to the memory device;

generating a command address signal to operate the memory device;

transmitting the command address signal in response to the clock; and

transmitting data to and receive data from the memory device through a data channel according to a transmission signaling mode selected from a first transmission signaling mode and a second transmission signaling mode,

wherein flag information, associated with at least one mode parameter, is received from the memory device during a training period of the memory device, and one of the first transmission signaling mode and the second transmission signaling mode is determined to be the transmission signaling mode using the flag information.

11. The method of claim 10 , further comprising making a training request for the data channel.

12. The method of claim 10 , wherein the first transmission signaling mode is a non-return-to-zero (NRZ) mode, and the second transmission signaling mode is a pulse amplitude modulation 4-level (PAM4) mode.

13. The method of claim 10 , further comprising:

generating a command address reference signal corresponding to the command address signal;

storing the command address reference signal;

comparing the stored command address reference signal with the command address reference signal received from the memory device; and

adjusting a phase or timing of the command address signal based on a comparison result of the comparator.

14. The method of claim 10 , wherein the transmission signaling mode varies, in real time, according to environment information of the data channel.

15. The method of claim 10 , further comprising making a training request for the data channel, and wherein the transmission signaling mode is detected by the memory device according to the training request.

16. A method of operating a controller configured to control a memory device, the method comprising:

transmitting a training request on a data channel to the memory device;

receiving flag information associated with at least one mode parameter from the memory device;

selecting a transmission signaling mode selected from a first transmission signaling mode and a second transmission signaling mode according to the at least one mode parameter; and

transmitting MRS (Mode Resister Set) information to the memory device according to the flag information,

wherein the first transmission signaling mode is a non-return-to-zero (NRZ) mode, and the second transmission signaling mode is a pulse amplitude modulation 4-level (PAM4) mode.

17. The method of claim 16 , wherein the least one mode parameter includes consumed current, a termination voltage, or channel loss associated with the data channel.

18. The method of claim 16 , further comprising storing the flag information in a mode resister.

19. The method of claim 16 , further comprising generating one bit of data, corresponding to each of a first voltage level and a second voltage level higher than the first voltage level, is transmitted through the data channel according to the first transmission signaling mode.

20. The method of claim 16 , wherein comprising generating two bits of data, corresponding to each of a first voltage level, a second voltage level higher than the first voltage level, a third voltage level higher than the second voltage level, and a fourth voltage level higher than the third voltage level, are transmitted through the data channel according to the second transmission signaling mode.