System and method of replicating and cancelling chopping folding error in delta-sigma modulators
A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.
1. A delta-sigma modulator, comprising:
a loop filter coupled to a quantizer having an output providing a digital signal;
chopper circuitry coupled to the loop filter configured to chop analog signals of the loop filter at a chopping frequency;
chopping folding error cancellation circuitry that is configured to replicate a chopping folding error of the chopper circuitry and to subtract the replicated chopping folding error from the digital signal to provide a corrected digital signal, the chopping folding error cancellation circuitry comprises:
chopping error circuitry configured to chop at the chopping frequency having an input for receiving the digital signal and having an output for providing the replicated chopping folding error of the chopper circuitry; and
a digital adder that is configured to subtract the duplicate chopping folding error from the digital signal for providing the corrected digital signal; and
calibration circuitry configured to calibrate the chopping error circuitry.
2. The delta-sigma modulator of claim 1 , wherein the chopping error circuitry comprises:
a digital chopper that is configured to chop the digital signal at the chopping frequency for providing a chopped digital signal; and
a digital amplifier that is configured to amplify the chopped digital signal by a gain value for providing the replicated chopping folding error.
3. The delta-sigma modulator of claim 1 , wherein the chopping error circuitry comprises:
a first digital multiplier that is configured to multiply the digital signal by a digital clock operating at the chopping frequency for providing the chopped digital signal; and
a second digital multiplier having a first input for receiving the chopped digital signal, having a second input receiving the gain value, and having an output providing the duplicate chopping folding error.
4. The delta-sigma modulator of claim 1 , further comprising adjust circuitry that is configured to adjust a digital chop clock operative at the chopping frequency.
5. The delta-sigma modulator of claim 4 , wherein the adjust circuitry comprises at least one of timing circuitry configured to adjust timing of the digital chop clock and duty cycle circuitry that is configured to adjust a duty cycle of the digital chop clock.
6. The delta-sigma modulator of claim 1 , wherein the chopping error circuitry comprises:
a digital chopper that is configured to chop the digital signal at the chopping frequency for providing a chopped digital signal; and
a digital filter that is configured to filter the chopped digital signal for providing the duplicate chopping folding error.
7. The delta-sigma modulator of claim 6 , wherein the digital filter comprises at either one of an infinite impulse response filter and a finite impulse response filter.
8. The delta-sigma modulator of claim 1 , wherein the chopping error circuitry comprises a digital filter and wherein the calibration circuitry is configured to calibrate the digital filter.
9. The delta-sigma modulator of claim 1 , further comprising timing circuitry that is configured to adjust timing of the chopping frequency and duty cycle circuitry that is configured to adjust a duty cycle of the chopping frequency, wherein the calibration circuitry is configured to calibrate the timing circuitry and the duty cycle circuitry.
10. The delta-sigma modulator of claim 1 , further comprising a decimation filter that filters and decimates the digital signal provided to the chopping folding error cancellation circuitry.
11. A method, comprising:
converting an input signal with a delta-sigma modulator comprising a loop filter coupled to a quantizer having an output for providing a digital signal;
chopping analog signals of the loop filter at a chopping frequency;
replicating a chopping folding error generated by the chopping of the analog signals based on digitally chopping the digital signal at the chopping frequency, the replicating comprising:
chopping the digital signal at the chopping frequency and providing a chopped digital signal; and
amplifying the chopped digital signal by a gain value for providing the replicated chopping folding error; and
subtracting the replicated chopping folding error from the digital signal and providing a corrected digital signal.
12. The method of claim 11 , wherein the amplifying comprises multiplying the chopped digital signal by a gain value for providing the replicated chopping folding error.
13. The method of claim 12 , wherein the replicating comprises:
chopping the digital signal at the chopping frequency and providing a chopped digital signal; and
filtering the chopped digital signal for providing the replicated chopping folding error.
14. The method of claim 13 , wherein the filtering comprises filtering using either one of an infinite impulse response filter and a finite impulse response filter.
15. The method of claim 11 , further comprising adjusting timing of a digital chop clock used for chopping the digital signal.
16. The method of claim 11 , further comprising adjusting a duty cycle of a digital chop clock used for chopping the digital signal.
17. The method of claim 11 , further comprising calibrating circuitry used for the replicating.
18. A method, comprising:
converting an input signal with a delta-sigma modulator comprising a loop filter coupled to a quantizer having an output for providing a digital signal;
chopping analog signals of the loop filter at a chopping frequency;
replicating a chopping folding error generated by the chopping of the analog signals based on digitally chopping the digital signal at the chopping frequency;
calibrating circuitry used for the replicating; and
subtracting the replicated chopping folding error from the digital signal and providing a corrected digital signal.
19. The method of claim 18 , wherein the amplifying comprises multiplying the chopped digital signal by a gain value for providing the replicated chopping folding error.
20. The method of claim 18 , further comprising adjusting timing of a digital chop clock used for chopping the digital signal.