Method of manufacturing a semiconductor structure
A method of manufacturing a semiconductor structure includes providing a substrate having an active region surrounded by an isolation layer; forming a first trench and a second trench in the active region, and a third trench and a fourth trench in the isolation layer; forming a bottom work-function layer in the third trench and the fourth trench, respectively; forming a middle work-function layer on the bottom work-function layer and in the first and the second trenches; forming a top work-function layer on the middle work-function layer; and forming a capping layer on the top work-function layer that fills a remaining region of the first, the second, the third and the fourth trenches.
1. A method of manufacturing a semiconductor structure, comprising:
providing a substrate having an active region surrounded by an isolation layer;
forming a first trench and a second trench in the active region, and a third trench and a fourth trench in the isolation layer;
forming a bottom work-function layer in the third trench and the fourth trench, respectively;
forming a middle work-function layer on the bottom work-function layer and in the first and the second trenches;
forming a top work-function layer on the middle work-function layer; and
forming a capping layer on the top work-function layer that fills a remaining region of the first, the second, the third and the fourth trenches.
2. The method of claim 1 , wherein the substrate comprises a first type semiconductor layer and a second type semiconductor layer on the first type semiconductor layer.
3. The method of claim 1 , wherein each of the third and the fourth trenches has a depth that is greater than a depth of each of the first and the second trenches.
4. The method of claim 1 , further comprising forming a dielectric layer on inner surfaces of the first and the second trenches before forming the bottom work-function layer.
5. The method of claim 1 , wherein the middle work-function layer has a work-function that is higher than a work-function of the first and the top work-function layers.
6. The method of claim 1 , wherein a top surface of the bottom work-function layer in the third and the fourth trench and a bottom of the middle work-function layer in the first and the second trench are at same horizontal level.
7. The method of claim 1 , further comprising forming a doped region in the active region between the first and the second trenches.
8. The method of claim 7 , further comprising forming a bit line contact electrically connected to the doped region.
9. The method of claim 1 , further comprising forming capacitors on a top surface of the active region between the isolation layer and the first and the second trenches respectively.