High-speed functional protocol based test and debug

1. An integrated circuit (IC) device comprising:

test control circuitry comprising test access port (TAP) circuitry and scan chain circuitry; and

a test controller electrically coupled with the test control circuitry, the test controller comprising:

packet decoder circuitry configured to decode packetized test pattern data to identify configuration data for the test controller and test data for the test control circuitry;

TAP bridge circuitry connected to the packet decoder circuitry and configured to receive the test data and communicate the test data to the TAP circuitry of the test control circuitry; and

scan bridge circuitry connected to the packet decoder circuitry and configured to receive the test data and communicate the test data to the scan chain circuitry of the test control circuitry, wherein the test controller is configured to packetize resulting data received from the test control circuitry, wherein the resulting data corresponds to errors identified by a test performed based on the test data.

2. The IC device of claim 1 further comprising:

a communication device configured to:

receive the packetized test pattern data from a testing device; and

communicate the packetized test pattern data to the test controller.

3. The IC device of claim 1 , wherein the test data corresponds to one of the TAP circuitry and the scan chain circuitry.

4. The IC device of claim 1 , wherein the test controller further comprises:

packet encoder circuitry connected to the TAP bridge circuitry and the scan bridge circuitry, the packet encoder circuitry is configured to:

receive resulting data from the TAP bridge circuitry and the scan bridge circuitry;

packetize the resulting data; and

output the packetized resulting data to a testing device.

5. The IC device of claim 1 , wherein the packet decoder circuitry is further configured to accumulate packetized test pattern data before decoding the packetized test pattern data.

6. A method comprising:

receive packetized test pattern data from a test device;

decode, via packet decoder circuitry of a test controller of an integrated circuit (IC) device, the packetized test pattern data to identify configuration data for the test controller and test data;

communicate, via test access port (TAP) bridge circuitry of the test controller, the test data to TAP circuitry of test control circuitry;

communicate, via scan bridge circuitry of the test controller, the test data to scan chain circuitry of the test control circuitry;

packetize resulting data received from the test control circuitry, wherein the resulting data corresponds to errors identified by a test performed within the IC device based on the test data; and

output the packetized resulting data from the IC device to the test device.

7. The method of claim 6 , wherein the packetized test pattern data is received via a communication device of the IC device, and the method further comprises communicating the packetized test pattern data from the communication device to the test controller.

8. The method of claim 6 , wherein the test data corresponds to one of the TAP circuitry and the scan chain circuitry.

9. The method of claim 8 further comprising accumulating packetized test pattern data before decoding the packetized test pattern data.

10. The method of claim 6 further comprising:

receiving, via packet encoder circuitry of the test controller, the resulting data from the TAP bridge circuitry and the scan bridge circuitry, wherein the packet encoder circuitry is configured to packetize the resulting data.

11. A test controller of an integrated circuit (IC) device comprising:

interconnect bridge circuitry configured to receive packetized test pattern data; and

test bridge circuitry comprising:

packet decoder circuitry configured to decode the packetized test pattern data to identify configuration data and test data for test control circuitry of the IC device;

test access port (TAP) bridge circuitry configured to receive the test data from the packet decoder circuitry and communicate the test data to TAP circuitry of the test control circuitry;

scan bridge circuitry configured to receive the test data and communicate the test data to scan chain circuitry of the test control circuitry; and

packetize resulting data received from the test control circuitry, wherein the resulting data corresponds to errors identified by a test performed based on the test data.

12. The test controller of claim 11 , wherein the packetized test pattern data is received by a communication device from a test device, and wherein the communication device is connected the interconnect bridge circuitry and is configured to communicate the packetized test pattern data to the test bridge circuitry via the interconnect bridge circuitry.

13. The test controller of claim 11 , wherein the test data corresponds to one of the TAP circuitry and the scan chain circuitry.

14. The test controller of claim 11 , wherein the test bridge circuitry further comprises:

packet encoder circuitry connected to the TAP bridge circuitry and the scan bridge circuitry, the packet encoder circuitry is configured to:

receive resulting data from the TAP bridge circuitry and the scan bridge circuitry;

packetize the resulting data; and

output the packetized resulting data to a test device.