Enhanced data clock operations in memory

1. A memory, comprising;

a memory array;

a memory I/O module configured to receive a data clock from a host via a link and output an internal data clock, wherein the internal data clock is in synchronization with the data clock from the host, and wherein the memory is configured to read from the memory array or write to the memory array based on the toggling of the internal data clock; and

a command decoder configured to detect a data clock suspend command while the internal data clock is synchronized with the data clock from the host, wherein the data clock suspend command comprises operands of WS_WR and WS_FS at logic one and WS_RD at logic zero, and wherein the internal data clock is configured to disable toggling in response to the command decoder detecting the data clock suspend command; the command decoder is further configured to detect a read or write command subsequent to detecting the data clock suspend command, and the internal data clock is further configured to start toggling based on the data clock from the host in response to the command decoder detecting the read or write command.

2. The memory of claim 1 is configured to perform a read or write operation in response to the read or write command.

3. The memory of claim 1 further comprises a memory mode register configured to store information of the data clock suspend command.

4. The memory of claim 3 , wherein the information of the data clock suspend command indicates whether the memory supports the data clock suspend command.

5. The memory of claim 1 , wherein the memory I/O module is configured to receive the toggling of the data clock after receiving the data clock suspend command.

6. The memory of claim 1 , wherein the internal data clock is coupled to the data clock by a clock buffer.

7. The memory of claim 6 , wherein the clock buffer is configured to be disabled to disable the toggling of the internal data clock.

8. An apparatus, comprising:

a host coupled to a memory via a link, wherein the host is configured to synchronize a data clock from the host with an internal data clock of the memory and to output write data or capture read data based on the internal data clock,

wherein the host comprises a memory controller configured

to provide a data clock suspend command to the memory via the link while the internal data clock is synchronized between the host and the memory, wherein the data clock suspend command notifies the memory to disable toggling the internal data clock, the internal data clock being configured to toggle based on the data clock from the host,

to toggle the data clock after providing the data clock suspend command,

to provide a read or write command to the memory via the link, subsequent to providing the data clock suspend command, wherein the read or write command notifies the memory to start toggling the internal data clock, and

to provide the read or write command to access the memory, without performing synchronization of the internal data clock and the data clock from the host between providing the data clock suspend command and providing the read or write command.

9. The apparatus of claim 8 , wherein the memory controller is configured to provide a mode register read command to the memory via the link, for information of the data clock suspend command, and configured to provide the data clock suspend command based on the information of the data clock suspend command.

10. The apparatus of claim 9 , wherein the information of the data clock suspend command indicates whether the memory supports the data clock suspend command.

11. The apparatus of claim 8 , wherein the memory controller is configured to operate in accordance with a low power double data rate dynamic random-access memory specification.

12. The apparatus of claim 11 , wherein the data clock suspend command comprises operands of WS_WR and WS_FS at logic one and WS_RD at logic zero.

13. The apparatus of claim 12 , wherein the memory comprises an LPDDR5 memory.

14. The apparatus of claim 13 , wherein the read or write command is between a first time period and a second time period after the data clock suspend command.

15. A method to reduce power of an internal data clock for a memory coupled to a host via a link, comprising:

receiving a data clock from a host, by the memory, via the link;

synchronizing, by the memory, the internal data clock with the data clock from the host;

toggling, by the memory, the internal data clock based on the data clock from the host to capture write data or to output read data;

detecting, by the memory, a data clock suspend command while the internal data clock is synchronized between the memory and the host, wherein the data clock suspend command comprises operands of WS_WR and WS_FS at logic one and WS_RD at logic zero;

disabling toggling of the internal data clock based on the data clock from the host, in response to detecting the data clock suspend command;

detecting, by the memory, a read or write command subsequent to detecting the data clock suspend command;

starting toggling the internal data clock based on the data clock from the host in response to detecting the read or write command; and

performing a read or write operation, by the memory, in response to the read or write command.

16. The method of claim 15 , further comprising storing, by a memory mode register, information of the data clock suspend command.

17. The method of claim 16 , wherein the information of the data clock suspend command indicates whether the memory supports the data clock suspend command.

18. A method, comprising:

providing, by a host to a memory via a link, a data clock from the host to a memory, wherein the memory is configured to toggle an internal data clock based on the data clock from the host to capture write data or to output read data;

providing, by the host to the memory via the link, a data clock suspend command, while the internal data clock is synchronized between the host and the memory, wherein the data clock suspend command comprises operands of WS_WR and WS_FS at logic one and WS_RD at logic zero, and wherein the memory is configured to disable toggling of the internal data clock in response to the data clock suspend command; and

providing, by the host to the memory via the link, a read or write command after the data clock suspend command, wherein the memory is configured to start toggling the internal data clock in response to the read or write command and to perform the read or write operation in response to the read or write command.

19. The method of claim 18 further comprising

providing, by the host to the memory via the link, a mode register read command; and

receiving, from the memory by the host via the link, information of the data clock suspend command in response to the mode register read command, wherein the information of the data clock suspend command indicates whether the memory supports the data clock suspend command.

20. The method of claim 18 further comprising determining, by the host, whether to providing, the data clock suspend command to the memory based on types, numbers, timing of commands, or instructions stored in a memory access queue module.

21. The method of claim 18 , wherein providing the read or write command after the data clock suspend command is between a first time period and a second time period after providing the data clock suspend command.

22. The method of claim 21 further comprising providing, by the host to the memory via the link, a command to instruct the memory to exit a data clock synchronization after providing the read or write command.

23. The method of claim 22 , wherein providing the command to instruct the memory to exit a data clock synchronization is done if a next read or write command is longer than the second time period of a previous read or write command.

24. The method of claim 21 , wherein the first time period and the second time period are determined based on power saving.