IP Library Granted Patent US 11,663,073
Granted Patent B2
US 11,663,073 · App. 17/118,434 · Granted May 30, 2023

Method and apparatus for data protection in memory devices

Inventors: SeyedMohammad SeyedzadehDelcheh (Bellevue, WA); Sergey Blagodurov (Bellevue, WA)
Assignee: Advanced Micro Devices, Inc.
G06F11/10
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Quick Facts
Patent No.
US 11,663,073
App. No.
17/118,434
Granted
May 30, 2023
Kind
B2
Abstract

An apparatus and method for efficiently transmitting data are described. A transmitter sends data to a receiver. An encoder of the transmitter divides a received first block of data into multiple sub-blocks. The encoder selects a portion of each sub-block to compare to one another. A portion in a particular sub-block has a same offset and a same size as other portions of other sub-blocks. If the encoder determines the multiple portions match one another, the encoder sends, to the receiver, a second block of data corresponding to the first block of data. The second block of data has a same size as a size of the received first block of data, and the second block of data includes security data from one of multiple error correction schemes. Therefore, the second block of data provides security without increasing an amount of data to transmit.

Claims (60)

1. A circuit comprising:

an interface comprising circuitry configured to receive a first block of data to transmit;

circuitry configured to:

divide the first block of data into a first plurality of sub-blocks of data;

generate a second block of data comprising a sub-block of data for each of the first plurality of sub-blocks of data, wherein the second block of data:

includes a sub-block of data that does not include at least a portion of data of a corresponding sub-block of the first plurality of sub-blocks, responsive to the portion of data matching a portion of data in another sub-block of the first plurality of sub-blocks of data;

comprises security data generated using an error correction scheme; and

has a size that is no greater than a size of the first block of data.

2. The circuit as recited in claim 1 , wherein the second block of data comprises a same number of sub-blocks as the first block of data.

3. The circuit as recited in claim 1 , wherein the error correction scheme generates code words with a size equal to a size of a sub-block of the first plurality of sub-blocks.

4. The circuit as recited in claim 1 , wherein the second block of data has a same size as the first block of data.

5. The circuit as recited in claim 1 , wherein the circuitry is configured to:

generate a third block of data by removing, from the first block of data, one or more portions that match one another;

determine a given size by dividing a size of the third block of data by a number of the plurality of sub-blocks; and

select the error correction scheme from a plurality of error correction schemes based at least in part on a determination that the given size matches a data input size of the error correction scheme.

6. The circuit as recited in claim 1 , wherein the circuitry is configured to:

select the error correction scheme based at least in part on the size of the second block of data less a size of the security data; and

use the error correction scheme to generate security data to include in the second block of data.

7. The circuit as recited in claim 6 , wherein the circuitry is configured to insert an indication in metadata of the second block of data specifying the error correction scheme.

8. The circuit as recited in claim 1 , based at least in part on a determination that no portions of the first plurality of sub-blocks match one another, generate a third block of data corresponding to the first block of data, wherein the third block of data has a larger size than a size of the first block of data.

9. A method comprising:

receiving, by an interface, a first block of data to transmit;

dividing, by a control unit, the first block of data into a first plurality of sub-blocks of data;

generating, by the control unit, a second block of data corresponding to the first block of data, wherein the second block of data:

includes a sub-block of data that does not include at least a portion of data of a corresponding sub-block of the first plurality of sub-blocks, responsive to the portion of data matching a portion of data in another sub-block of the first plurality of sub-blocks of data;

comprises security data generated using an error correction scheme; and

has a size that is no greater than the first block of data.

10. The method as recited in claim 9 , further comprising generating the second block of data with a same number of sub-blocks as the first block of data.

11. The method as recited in claim 9 , further comprising generating the second block of data to have a same size as the first block of data.

12. The method as recited in claim 9 , further comprising:

generating a third block of data by removing, from the first block of data, one or more portions of the first plurality of sub-blocks of data that match one another;

determining a given size by dividing a size of the third block of data by a number of the plurality of sub-blocks; and

selecting the error correction scheme from a plurality of error correction schemes based at least in part on a determination that the given size matches a data input size of the error correction scheme.

13. The method as recited in claim 9 , further comprising:

selecting the error correction scheme from a plurality of error correction schemes based at least upon the size of the second block of data less a size of the security data; and

using the error correction scheme to generate security data to include in the second block of data.

14. The method as recited in claim 13 , further comprising inserting an indication in metadata of the second block of data specifying the error correction scheme.

15. The method as recited in claim 9 , wherein, in response to determining that no portions of first plurality of sub-blocks of data match one another, generating a third block of data corresponding to the first block of data, wherein the third block of data has a larger size than a size of the first block of data.

16. An apparatus comprising:

a plurality of transmitters comprising circuitry configured to send blocks of data;

a plurality of receivers comprising circuitry configured to receive blocks of data;

wherein one or more of the plurality of transmitters comprises an encoder;

wherein the encoder comprising circuitry comprises:

an interface configured to receive a first block of data to transmit;

an error correction unit comprising circuitry configured to support a plurality of error correction schemes, each scheme is configured to generate security data corresponding to data to transmit; and

a control unit comprising circuitry configured to:

divide the first block of data into a first plurality of sub-blocks of data;

generate a second block of data comprising a sub-block of data for each of the first plurality of sub-blocks of data, wherein the second block of data:

includes a sub-block of data that does not include at least a portion of data of a corresponding sub-block of the first plurality of sub-blocks, responsive to the portion of data matching a portion of data in another sub-block of the first plurality of sub-blocks of data;

comprises security data generated by the control unit using an error correction scheme; and

has a size that is no greater than the first block of data.

17. The apparatus as recited in claim 16 , wherein the second block of data comprises a same number of sub-blocks as the first block of data.

18. The apparatus as recited in claim 16 , wherein the second block of data has a same size as the first block of data.

19. The apparatus as recited in claim 16 , wherein the control unit is configured to:

generate a third block of data by removing, from the first block, one or more portions of the first plurality of sub-blocks of data match one another;

determine a given size by dividing a size of the third block of data by a number of the plurality of sub-blocks; and

select a given error correction scheme of the plurality of error correction schemes based at least in part on a determination that the given size matches a data input size of the given error correction scheme.

20. The apparatus as recited in claim 16 , wherein the control unit is configured to:

select a given error correction scheme of the plurality of error correction schemes based at least in part on the size of the second block of data less a size of the security data; and

use the given error correction scheme to generate security data to include in the second block of data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 10, 2020
From: SEYEDZADEHDELCHEH, SEYEDMOHAMMAD; BLAGODUROV, SERGEY
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 054611/0537 →
Continuity (1)
Related Publication 20220188185A1 · Jun 16, 2022