Integrated circuit devices including stacked transistors
Integrated circuit devices may include a lower transistor and an upper transistor stacked on a substrate and may include a conductive contact. The upper transistor may include an upper source/drain region that overlaps a lower source/drain region of the lower transistor. The conductive contact may contact a side surface of the upper source/drain region and may overlap a center portion of the lower source/drain region. The side surface of the upper source/drain region may include a protrusion and a recess.
1. An integrated circuit device comprising:
an upper transistor on a substrate, the upper transistor comprising an upper active region and first and second upper source/drain regions that are spaced apart from each other in a first horizontal direction, wherein each of the first and second upper source/drain regions comprises a first side surface contacting a respective one of opposing side surfaces of the upper active region and a second side surface spaced apart from the first side surface in the first horizontal direction, and the first horizontal direction is parallel to an upper surface of the substrate;
a lower transistor between the substrate and the upper transistor, the lower transistor comprising a lower active region and first and second lower source/drain regions that are spaced apart from each other in the first horizontal direction and contact opposing side surfaces of the lower active region, respectively, wherein the first upper source/drain region overlaps the first lower source/drain region in a vertical direction that is perpendicular to the upper surface of the substrate, and the first lower source/drain region comprises a center portion in a second horizontal direction that is perpendicular to the first horizontal direction and is parallel to the upper surface of the substrate; and
a conductive contact that contacts and overlaps the second side surface of the first upper source/drain region and overlaps the center portion of the first lower source/drain region in the vertical direction.
2. The integrated circuit device of claim 1 , wherein the first lower source/drain region comprises opposing side surfaces that are spaced apart from each other in the second horizontal direction, and
a center of the conductive contact in the second horizontal direction is equidistant from the opposing side surfaces of the first lower source/drain region.
3. The integrated circuit device of claim 1 , wherein an entirety of the conductive contact overlaps the first lower source/drain region in the vertical direction.
4. The integrated circuit device of claim 1 , wherein the first lower source/drain region has a first width in the second horizontal direction, the conductive contact has a second width in the second horizontal direction, and the first width is wider than the second width.
5. The integrated circuit device of claim 1 , wherein the first upper source/drain region comprises a protrusion that protrudes in the first horizontal direction into the conductive contact.
6. The integrated circuit device of claim 5 , wherein the protrusion tapers toward the conductive contact.
7. The integrated circuit device of claim 1 , wherein the second side surface of the first upper source/drain region comprises a recess that is recessed toward the first upper source/drain region, and a portion of the conductive contact is in the recess.
8. The integrated circuit device of claim 1 , wherein the conductive contact contacts the center portion of the first lower source/drain region.
9. The integrated circuit device of claim 1 , wherein the upper active region comprises a plurality of nanosheet layers that are stacked in the vertical direction.
10. The integrated circuit device of claim 1 , wherein the upper transistor further comprises an upper gate electrode, and the lower transistor further comprises a lower gate electrode that is electrically connected to the upper gate electrode.
11. An integrated circuit device comprising:
a first upper transistor and a second upper transistor on a substrate, wherein the first and second upper transistors are spaced apart from each other in a first horizontal direction that is parallel to an upper surface of the substrate, each of the first and second upper transistors comprises an upper active region and an upper source/drain region that comprises a first surface contacting the upper active region and a second surface opposite the first surface, and the second surfaces of the upper source/drain regions are spaced apart from each other in the first horizontal direction;
a first lower transistor and a second lower transistor between the substrate and the first and second upper transistors, each of the first and second lower transistors comprising a lower active region and a lower source/drain region contacting the lower active region; and
a conductive contact that contacts the second surfaces of the upper source/drain regions,
wherein each of the upper source/drain regions comprises a protrusion that protrudes into the conductive contact.
12. The integrated circuit device of claim 11 , wherein the protrusions taper toward the conductive contact.
13. The integrated circuit device of claim 11 , wherein each of the second surfaces of the upper source/drain regions comprises a recess, and portions of the conductive contact are in the recesses.
14. A method of forming an integrated circuit device, the method comprising:
forming a first lower transistor and a second lower transistor on a substrate, each of the first and second lower transistors comprising a lower active region and a lower source/drain region contacting the lower active region;
forming a first upper transistor and a second upper transistor on the first and second lower transistors, wherein the first and second upper transistors are spaced apart from each other in a first horizontal direction that is parallel to an upper surface of the substrate, each of the first and second upper transistors comprises an upper active region and an upper source/drain region that comprises a first surface contacting the upper active region and a second surface opposite the first surface, and the second surfaces of the upper source/drain regions are spaced apart from each other in the first horizontal direction;
forming an insulating layer on the first and second upper transistors, the insulating layer separating the second surfaces of the upper source/drain regions from each other;
forming an opening in the insulating layer, the opening exposing the second surfaces of the upper source/drain regions; and
forming a conductive contact in the opening.
15. The method of claim 14 , wherein forming the opening comprises removing a portion of the insulating layer while maintaining shapes of the second surfaces of the upper source/drain regions.
16. The method of claim 14 , wherein each of the lower source/drain regions is a portion of a common lower source/drain region, and
the common lower source/drain region has a first width in the first horizontal direction, each of the upper source/drain regions has a second width in the first horizontal direction, and the second width is narrower than half of the first width.
17. The method of claim 14 , wherein each of the lower source/drain regions is a portion of a common lower source/drain region,
the opening of the insulating layer exposes an upper portion of the common lower source/drain region, and
the conductive contact contacts the upper portion of the common lower source/drain region.
18. The method of claim 14 , wherein the upper source/drain regions are formed by an epitaxial growth process using the upper active regions as a seed layer, and each of the second surfaces of the upper source/drain regions comprises a recess.
19. The method of claim 18 , wherein forming the conductive contact in the opening comprises forming the conductive contact in the recesses of the second surfaces of the upper source/drain regions.