Semiconductor package including antenna substrate and manufacturing method thereof

1. A semiconductor package comprising:

a package substrate including an upper surface;

a chip disposed adjacent to the upper surface of the package substrate;

a plurality of wires electrically connecting the chip with the package substrate;

an antenna substrate disposed on the chip; and

a spacer disposed over the chip and between the antenna substrate and the package substrate, wherein the spacer is spaced apart from the wires by a gap.

2. The semiconductor package of claim 1 , wherein the wires comprise bond wires, a lateral surface of the spacer is recessed from a lateral surface of the antenna substrate to define a cavity to accommodate the bond wires, a first end of the bond wires is connected to the chip, a second end of the bond wires is connected to the package substrate, and the chip is disposed between the package substrate and the antenna substrate.

3. The semiconductor package of claim 2 , wherein a first portion of the bond wires are under a projection of the antenna substrate, and a second portion of the bond wires are outside of the projection of the antenna substrate.

4. The semiconductor package of claim 3 , wherein a topmost portion of the bond wires are at an elevation lower than that of a topmost surface of the spacer, and a bottom portion of the bond wires is at an elevation lower than an elevation of a bottommost surface of the spacer.

5. The semiconductor package of claim 4 , further comprising a package body encapsulating the bond wires, the chip, the antenna substrate and the spacer;

wherein the antenna substrate comprises an antenna layer having an upper surface facing away from the chip and angled with the lateral surface of the antenna substrate, and the package body encapsulates the lateral surface of the antenna substrate and exposes the upper surface of the antenna layer.

6. The semiconductor package of claim 5 , wherein:

the antenna substrate includes:

a core layer including a grounding conductive via and a feeding conductive via;

a grounding layer disposed on a lower surface of the core layer, the grounding layer including a feeding portion and a grounding portion; and

an antenna layer including a grounding portion and an antenna portion, wherein the grounding portion of the antenna layer electrically connects with the grounding portion of the grounding layer of the antenna substrate by the grounding conductive via of the core layer, the antenna portion of the antenna layer electrically connects with the feeding portion of the grounding layer of the antenna substrate by the feeding conductive via of the core layer, the grounding portion and the antenna portion are disposed on the same surface of the core layer, and the grounding portion is spaced apart from the antenna portion.

7. The semiconductor package of claim 6 ,

wherein the grounding layer is disposed on the lower surface of the core layer, and the grounding portion surrounds the feeding portion and is spaced from the feeding portion;

wherein the antenna layer is disposed on an upper surface of the core layer and electrically connected with the feeding portion by the feeding conductive via;

wherein the spacer includes an upper surface, a feeding layer, a grounding layer, a feeding conductive via and a grounding conductive via, the feeding layer and the grounding layer of the spacer are disposed on the upper surface of the spacer;

wherein the feeding portion of the grounding layer of the antenna substrate electrically connects with the chip by the feeding layer of the spacer and the feeding conductive via of the spacer, the grounding portion of the grounding layer of the antenna substrate electrically connects with the chip by the grounding layer of the spacer and the grounding conductive via of the spacer; and

wherein the feeding conductive layer of the core layer of the antenna substrate is spaced apart from the feeding layer of the spacer, a width of the feeding layer of the spacer is greater than a width of the feeding conductive layer of the core layer of the antenna substrate, the grounding layer of the antenna substrate contacts the grounding layer of the spacer, and a surface of the grounding layer of the antenna substrate and a surface of the grounding layer of the spacer are at the same elevation.

8. A semiconductor package comprising:

a package substrate including an upper surface;

a semiconductor device disposed adjacent to the upper surface of the package substrate;

a passive component disposed adjacent to the upper surface of the package substrate;

an antenna substrate disposed on the semiconductor device, wherein the semiconductor device is electrically connected to the passive component through a trace adjacent to the upper surface of the package substrate; and

a ground potential layer disposed on the package substrate, wherein the grounding potential layer is located closer to the package substrate than the antenna substrate.

9. The semiconductor package of claim 8 , wherein the semiconductor device is electrically connected to the trace through a conductive bond wire, the antenna substrate comprises a grounding layer, and a portion of the conductive bond wire is exposed from the grounding layer.

10. The semiconductor package of claim 8 , further comprising a spacer disposed over the semiconductor device and between the antenna substrate and the package substrate, wherein the spacer is recessed from a lateral surface of the antenna substrate.

11. The semiconductor package of claim 10 , further comprising:

a wire electrically connecting the semiconductor device to the package substrate;

wherein the spacer is disposed between the antenna substrate and the package substrate to provide a space to accommodate the wire, and the spacer is spaced apart from the wire.

12. The semiconductor package of claim 11 , wherein the passive component is electrically connected to the package substrate sequentially through the trace, the wire, and the semiconductor device.

13. The semiconductor package of claim 12 , wherein the antenna substrate has a first surface facing the chip and a second surface opposite to the first surface, and the semiconductor package further comprises a package body covering the second surface of the antenna substrate.

14. The semiconductor package of claim 13 , wherein the antenna substrate further has a lateral surface extending between the first surface and the second surface, and the package body further covers the lateral surface of the antenna substrate.

15. The semiconductor package of claim 14 , further comprising a spacer disposed between the antenna substrate and the package substrate, and a portion of the package body extends between the spacer and the antenna substrate.

16. The semiconductor package of claim 15 , wherein the package body covers a lateral surface of the spacer.

17. The semiconductor package of claim 13 , wherein the antenna substrate includes a grounding layer, and the package body further covers a lateral surface of the grounding layer of the antenna substrate.

18. The semiconductor package of claim 17 , wherein the antenna substrate further includes an antenna layer, and a lateral surface of the antenna layer is coplanar with a lateral surface of the grounding layer.