IP Library Granted Patent US 11,664,658
Granted Patent B2
US 11,664,658 · App. 17/745,958 · Granted May 30, 2023

Electrostatic protection device

Inventors: Thomas Morf (Gross, CH); Pier Andrea Francese (Adliswil, CH)
Assignee: International Business Machines Corporation
H02H9/046H01L27/0248
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Quick Facts
Patent No.
US 11,664,658
App. No.
17/745,958
Granted
May 30, 2023
Kind
B2
Abstract

An electrostatic protection device for protecting an input port of an electronic circuit. The electrostatic protection device includes a first stacked coil, a second stacked coil, and an input terminal, wherein the second stacked coil is inductively coupled to the first stacked coil. The first stacked coil comprises a first coil input connected to the input terminal, and a first coil output port connected to a lower frequency ESD protection circuit, and wherein the lower frequency ESD protection circuit comprises a lower frequency output. The second stacked coil comprises an output port connected to a higher frequency ESD protection circuit, and wherein the higher frequency ESD protection circuit comprises a higher frequency output.

Claims (31)

1. An electrostatic protection device for protecting an input port of an electronic circuit, the electrostatic protection device comprising:

a first stacked coil, a second stacked coil, and an input terminal, wherein the second stacked coil is inductively coupled to the first stacked coil;

wherein the first stacked coil comprises a first coil input connected to the input terminal, and a first coil output port connected to a lower frequency ESD protection circuit, and wherein the lower frequency ESD protection circuit comprises a lower frequency output; and

wherein the second stacked coil comprises an output port connected to a higher frequency ESD protection circuit, and wherein the higher frequency ESD protection circuit comprises a higher frequency output.

2. The electrostatic protection device of claim 1 , wherein the first stacked coil and the second stacked coil form a crossover network configured to divide a signal input into the input terminal into a higher frequency component and a lower frequency component, wherein the higher frequency component being output by the higher frequency output and the lower frequency component being output by the lower frequency output.

3. The electrostatic protection device of claim 1 , wherein the first stacked coil further comprises a first coil termination port connected to a termination load.

4. The electrostatic protection device of claim 1 , wherein the first stacked coil is a T-coil with a single coil tap.

5. The electrostatic protection device of claim 4 , wherein the single coil tap divides the first stacked coil into a first coil portion and a second coil portion, the single coil tap is the first coil output, the second coil portion being connected between the single coil tap and the coil termination port, and the first coil portion being connected between the single coil tap and the first coil input.

6. The electrostatic protection device of claim 5 , wherein an inductive coupling between the first coil portion and the second stacked coil is greater than the inductive coupling between the second coil portion and the second stacked coil.

7. The electrostatic protection device of claim 6 , wherein the second stacked coil comprises a reference port connected to a ground plane of the electrostatic protection device.

8. The electrostatic protection device of claim 1 , wherein the lower frequency ESD protection circuit comprises a human body model ESD protection circuit.

9. The electrostatic protection device of claim 8 , wherein the lower frequency ESD protection comprises an additional charge device model ESD protection circuit.

10. The electrostatic protection device of claim 1 , wherein the first stacked coil comprises a first coil tap and a second coil tap, and the lower frequency ESD protection circuit is connected to the first coil tap and the second coil tap.

11. The electrostatic protection device of claim 10 , wherein the first stacked coil comprises a first coil portion, an intermediate coil portion, and a second coil portion, wherein the first coil portion is connected between the first coil input and the first coil tap, the intermediate coil portion is connected between the first coil tap and the second coil tap, and the second coil portion is connected between the second coil tap and the first coil termination port.

12. The electrostatic protection device of claim 11 , wherein the lower frequency ESD protection circuit comprises a human body model ESD protection circuit, the lower frequency ESD protection comprising an additional charge device model ESD protection circuit, the additional charge device model ESD protection circuit is connected to the first coil tap, and the human body model ESD protection circuit is connected to the second coil tap.

13. The electrostatic protection device of claim 1 , wherein the second stacked coil comprises a reference port connected to a ground plane of the electrostatic protection device.

14. The electrostatic protection device of claim 1 , wherein the second stacked coil comprising a reference port is connected to the second coil tap.

15. The electrostatic protection device of claim 1 , wherein the first stacked coil is at least partially formed from a top two metallization layers of the electrostatic protection device.

16. The electrostatic protection device of claim 1 , wherein the higher frequency ESD protection circuit comprises a primary charge device model ESD protection circuit.

17. The electrostatic protection device of claim 16 , wherein the primary charge device model ESD protection circuit has a primarily reactive impedance.

18. The electrostatic protection device of claim 1 , wherein the summation circuit is a Continuous Time Linear Equalizer circuit.

19. The electrostatic protection device of claim 18 , wherein the input port of the electronic circuit is a differential input port, where the differential input port is formed by two electrostatic protection devices connected together via the continuous time linear equalizer circuit.

20. The electrostatic protection device of claim 1 , wherein the summation circuit is formed from a summing amplifier.

21. The electrostatic protection device of claim 1 , wherein the termination load is resistive.

22. The electrostatic protection device of claim 1 , further comprising a summation circuit configured for outputting a summation of the higher frequency output and the lower frequency output to the input port of the electronic circuit.

23. An integrated circuit comprising an electronic circuit, the integrated circuit comprising an electrostatic protection device for protecting an input port of the electronic circuit, the electrostatic protection device comprising:

a first stacked coil, a second stacked coil, and an input terminal, wherein the second stacked coil is inductively coupled to the first stacked coil;

wherein the first stacked coil comprises a first coil input connected to the input terminal, and a first coil output port connected to a lower frequency ESD protection circuit, and wherein the lower frequency ESD protection circuit comprises a lower frequency output; and

wherein the second stacked coil comprises an output port connected to a higher frequency ESD protection circuit, and wherein the higher frequency ESD protection circuit comprises a higher frequency output.

24. The integrated circuit of claim 23 , wherein the integrated circuit is selected from a group consisting of: a microprocessor, a microcontroller, a graphical processing unit, a central processing unit, wide band amplifier, analog to digital converter, digital to analog converter, wireline transceiver circuit, and a telecommunications chip.

25. The integrated circuit of claim 23 , wherein the integrated circuit comprises a substrate, the electronic circuit being formed on the substrate, the electrostatic protection device being formed on the substrate, and the second stacked coil being formed closer to the substrate than the first stacked coil.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2022
From: MORF, THOMAS; FRANCESE, PIER ANDREA
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 059927/0650 →
Continuity (2)
Continuation 17208090 · Mar 22, 2021
Related Publication 20220302698A1 · Sep 22, 2022
Cited By (1)
US 12,414,382