IP Library › Granted Patent US 11,665,007
Granted Patent B2
US 11,665,007 · App. 16/852,629 · Granted May 30, 2023

PoE powered device with link layer startup processor

Inventors: Mark LaBosco (New City, NY); Marc Dubowski (Fishkill, NY); John Hartnett (Cortlandt Manor, NY)
Assignee: Crestron Electromics, Inc.
H04L12/10G06F1/266G06F1/28H04L12/12
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Quick Facts
Patent No.
US 11,665,007
App. No.
16/852,629
Granted
May 30, 2023
Kind
B2
Abstract

A Power over Ethernet (PoE) Powered Device ( 60 ) is described herein that includes an auxiliary processor ( 62 ) that negotiates a power level with a PoE Power Sourcing Equipment using a first link layer ( 650 ), means for holding the PoE Powered Device in a low power state, and a second link layer ( 50 ) that allows the main processor to communicate over the Ethernet.

Claims (61)

1. A Power over Ethernet (PoE) system comprising:

a PoE Power Sourcing Equipment (PSE), including a PSE Controller, connected to a first end of an Ethernet cable;

a PoE Powered Device (PD), including a PD Controller, connected to a second end of the Ethernet cable, wherein the PoE PD further comprises:

a main processor,

an auxiliary processor configured to negotiate a power level with the PoE Power Sourcing Equipment using a first data link layer in a communications process that is conducted as a software based link layer discovery protocol classification scheme, and further configured to hold the PoE Powered Device in a low power state, and

a second data link layer in a communications process that is conducted as a software based link layer discovery protocol classification scheme, wherein

the main processor is configured to communicate over the Ethernet cable using the second data link layer; and

a switching device configured to receive a signal from the auxiliary processor that transfers power from the auxiliary processor to the main processor after the power level negotiation.

2. The system according to claim 1 , wherein the switching device comprises:

a power relay configured to direct electrical power supplied by a DC-DC converter to either the main processor or the auxiliary processor.

3. The system according to claim 1 , wherein the switching device comprises:

a switching transistor configured to direct electrical power supplied by a DC-DC converter to either the main processor or the auxiliary processor.

4. A Power over Ethernet (PoE) Powered Device (PD) comprising:

a main processor;

an auxiliary processor configured to negotiate a power level with a PoE Power Sourcing Equipment using a first data link layer in a communications process that is conducted as a software based link layer discovery protocol classification scheme, and further configured to hold the PoE Powered Device in a low power state;

a second data link layer in the communications process that is conducted as a software based link layer discovery protocol classification scheme, wherein the main processor is configured for network communications using the second data link layer; and

a switching device configured to receive a signal from the auxiliary processor that transfers power from the auxiliary processor to the main processor after the power level negotiation.

5. The device according to claim 4 , further comprising:

a non-volatile memory associated with the auxiliary processor and configured to store a MAC address associated with the main processor, and a required PoE power level.

6. The device according to claim 4 , wherein the auxiliary processor is selected from the group consisting of a central processing unit (CPU) integrated circuit, and a state machine implemented on a field programmable gate array (FPGA).

7. The device according to claim 4 , wherein the switching device comprises:

a power relay configured to direct electrical power supplied by a DC-DC converter to either the main processor or the auxiliary processor.

8. The device according to claim 4 , wherein the switching device comprises:

a switching transistor configured to direct electrical power supplied by a DC-DC converter to either the main processor or the auxiliary processor.

9. The device of claim 4 , further comprising:

an inter-processor communication bus connected between the auxiliary processor and the main processor, and wherein;

the inter-processor communication bus is configured to transfer status information from the auxiliary processor to the main processor prior to transferring power.

10. The device of claim 9 , wherein

such status information includes at least one or more of negotiated speed, and duplex setting.

11. A powered device (PD) controller suitable for use within a Power over Ethernet (PoE) PD, the PD controller comprising:

powered device controller circuitry;

a physical medium dependent sublayer; and

a data switch operable to selectively connect either a first physical medium attachment sublayer or a second physical medium attachment sublayer to the physical medium dependent sublayer; and

a switching device configured to receive a signal from the auxiliary processor that transfers power from the auxiliary processor to the main processor after the power level negotiation.

12. The PD controller according to claim 11 , wherein each of the powered device controller circuitry, physical medium dependent sublayer, and data switch are collocated on an integrated circuit chip.

13. A method for initializing a Power over Ethernet (PoE) connection comprising:

(a) connecting a PoE power sourcing equipment (PSE) to a PoE powered device (PD), the PoE PSE comprising a PSE controller;

(b) performing, at the PSE controller, a first power level classification in accordance with IEEE 802.3af;

(c) booting up an auxiliary processor located in the PD;

(d) determining whether a second power level classification, in accordance with IEEE 802.3at, has been performed;

(e) negotiating, when the second power level classification has not been performed, by the auxiliary processor, a power level classification using a link layer discovery protocol (LLDP);

(f) booting up a main processor in the PD; and

(g) receiving a signal from the auxiliary processer at a switching device that transfers power from the auxiliary processor to the main processor after the power level negotiation.

14. The method according to claim 13 , further comprising:

enabling power to be sent to the main processor by the auxiliary processor prior to the step of booting up the main processor.

15. The method according to claim 13 , further comprising:

enabling a data transfer switch by the auxiliary processor subsequent to the step of booting up the main processor.

16. A Power over Ethernet (PoE) Powered Device (PD) comprising:

a main processor;

an auxiliary processor configured to negotiate a power level with a PoE Power Sourcing Equipment using a first data link layer in a communications process that is conducted as a software based link layer discovery protocol classification scheme, and further configured

to transfer power of the PoE Powered Device from a low power state to a high power state by transmitting a power transfer control signal to a power supply following the power level negotiation with the PoE Power Sourcing Equipment;

a second data link layer in the communications process that is conducted as a software based link layer discovery protocol classification scheme, wherein the main processor is configured for network communications using the second data link layer; and

a switching device configured to receive a signal from the auxiliary processor that transfers power from the auxiliary processor to the main processor after the power level negotiation.

17. The device according to claim 16 , further comprising:

a non-volatile memory associated with the auxiliary processor and configured to store a MAC address associated with the main processor, and a required PoE power level.

18. The device according to claim 16 , wherein the auxiliary processor is selected from the group consisting of a central processing unit (CPU) integrated circuit, and a state machine implemented on a field programmable gate array (FPGA).

19. The device of claim 16 , further comprising:

an inter-processor communication bus connected between the auxiliary processor and the main processor, and wherein

the inter-processor communication bus is configured to transfer status information from the auxiliary processor to the main processor prior to transferring power.

20. The device of claim 19 , wherein

such status information includes at least one or more of negotiated speed, and duplex setting.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2021
From: LABOSCO, MARK; DUBOWSKI, MARC; HARTNETT, JOHN
To: CRESTRON ELECTRONICS, INC.
Reel/Frame 056424/0452 →
Continuity (3)
Continuation 15843299 · Dec 15, 2017
Related Publication 20200244471A1 · Jul 30, 2020
Related Publication 20200244471A1 · Jul 30, 2020
Cited By (1)
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