Method for manufacturing semiconductor structure and capable of controlling thicknesses of oxide layers

1. A method for manufacturing a semiconductor structure, the method comprising:

forming a first oxide layer on a wafer;

forming a silicon nitride layer on the first oxide layer;

forming a plurality of trenches;

filling an oxide material in the trenches to form a plurality of shallow trench isolation regions;

performing a polishing process to planarize a surface of the silicon nitride layer;

removing the silicon nitride layer without removing the first oxide layer;

using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and

removing the second part of the first oxide layer while remaining the first part of the first oxide layer.

2. The method of claim 1 , further comprising:

removing the photoresist;

performing a first oxidation process to form a second oxide layer on the second area and increase a thickness of the first part of the first oxide layer;

implanting ions to form a plurality of well regions;

removing the second oxide layer; and

performing a second oxidation process to form a third oxide layer on the second area and increase the thickness of the first part of the first oxide layer.

3. The method of claim 2 , wherein the first oxide layer is a pad oxide layer, the second oxide layer is a sacrificial oxide layer, and the third oxide layer is a gate oxide layer of an input/output device.

4. The method of claim 2 , wherein the thickness of the first part of the first oxide layer is larger than a thickness of the third oxide layer after performing the second oxidation process.

5. The method of claim 2 , wherein each of the first oxidation process and the second oxidation process comprises one of a physical vapor deposition process, a chemical vapor deposition process, a plasma-enhanced chemical vapor deposition process and a thermal oxidation process.

6. The method of claim 1 , wherein the first area is corresponding to a memory device, and the second area is corresponding to an input/output device.

7. The method of claim 1 , wherein the polishing process comprises a chemical-mechanical polishing process.