IP Library › Granted Patent US 11,665,975
Granted Patent B2
US 11,665,975 · App. 16/012,673 · Granted May 30, 2023

Spin orbit coupling memory device with top spin orbit coupling electrode and selector

Inventors: Tanay Gosavi (Hillsboro, OR); Chia-Ching Lin (Portland, OR); Sasikanth Manipatruni (Portland, OR); Ian Young (Portland, OR)
Assignee: Intel Corporation
H01L43/02G11C11/161H01F10/329H01F10/3254H01F10/3286H01L27/224H01L27/228H01L43/10H01L43/12H01F10/3272
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Quick Facts
Patent No.
US 11,665,975
App. No.
16/012,673
Granted
May 30, 2023
Kind
B2
Abstract

An apparatus is provided which comprises: a bit-line; a first word-line; a second word-line; and a source-line; a magnetic junction comprising a free magnet; an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the free magnet of the magnetic junction; and a first device (e.g., a selector device) coupled at one end of the interconnect and to the second word-line; and a second device coupled to the magnetic junction, the first word-line and the source-line.

Claims (48)

1. An apparatus comprising:

a bit-line; a first word-line; a second word-line; and a source-line;

a magnetic junction comprising a free magnet;

an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the free magnet of the magnetic junction;

a first device coupled at one end of the interconnect, wherein the first device is coupled to the second word-line; and

a second device coupled to the magnetic junction, the first word-line, and the source-line, wherein the first device is a two-terminal selector device comprising metal and oxygen.

2. The apparatus of claim 1 , wherein the two-terminal selector device comprises:

a first structure comprising metal;

a second structure comprising oxygen; and

a third structure comprising metal, wherein the second structure is between the first and third structures.

3. The apparatus of claim 1 , wherein the interconnect is positioned in a backend-of-line (BEOL) of a die or near the BEOL of the die, and wherein the magnetic junction is closer to a frontend-of-line (FEOL) of the die compared to the interconnect.

4. The apparatus of claim 1 , wherein the free magnet has perpendicular magnetization relative to a plane of the apparatus.

5. The apparatus of claim 1 , wherein the free magnet comprises a material comprising one or more of Co, Fe, Ni, or O.

6. The apparatus of claim 1 , wherein the free magnet is one of a paramagnet or a ferromagnet.

7. The apparatus of claim 1 , comprising:

a processor;

a memory coupled to the processor, the memory comprising the bit-line, first and second word- lines, and source-line, magnetic junction, interconnect, and first and second devices; and

a wireless interface to allow the processor to communicate with another device.

8. An apparatus, comprising: a bit-line; a first word-line; a second word-line; and a source-line; a magnetic junction comprising a free magnet; an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the free magnet of the magnetic junction; a first device coupled at one end of the interconnect, wherein the first device is coupled to the second word-line; and a second device coupled to the magnetic junction, the first word-line, and the source-line, wherein the first device comprises one or more of Pt, Te, Mo, Se, S, Ti, Zn, In, Ga, Rh, Nb, or Sn.

9. The apparatus of claim 8 , wherein the first device comprises:

a first structure comprising metal;

a second structure comprising oxygen; and

a third structure comprising metal, wherein the second structure is between the first and third structures.

10. The apparatus of claim 8 , wherein the interconnect is positioned in a backend-of-line (BEOL) of a die or near the BEOL of the die, and wherein the magnetic junction is closer to a frontend-of-line (FEOL) of the die compared to the interconnect.

11. The apparatus of claim 8 , wherein the free magnet has perpendicular magnetization relative to a plane of the apparatus.

12. The apparatus of claim 8 , wherein the free magnet comprises a material comprising one or more of Co, Fe, Ni, or O.

13. The apparatus of claim 8 , wherein the free magnet is one of a paramagnet or a ferromagnet.

14. The apparatus of claim 8 , comprising:

a processor;

a memory coupled to the processor, the memory comprising the bit-line, first and second word- lines, and source-line, magnetic junction, interconnect, and first and second devices; and

a wireless interface to allow the processor to communicate with another device.

15. An apparatus, comprising:

a bit-line; a first word-line; a second word-line; and a source-line;

a magnetic junction comprising a free magnet;

an interconnect comprising spin orbit material, wherein the interconnect is adjacent to the free magnet of the magnetic junction;

a first device coupled at one end of the interconnect, wherein the first device is coupled to the second word-line; and

a second device coupled to the magnetic junction, the first word-line, and the source-line, wherein the interconnect is positioned in a backend-of-line (BEOL) of a die or near the BEOL of the die, and wherein the magnetic junction is closer to a frontend-of-line (FEOL) of the die compared to the interconnect.

16. The apparatus of claim 15 , wherein the first device comprises:

a first structure comprising metal;

a second structure comprising oxygen; and

a third structure comprising metal, wherein the second structure is between the first and third structures.

17. The apparatus of claim 15 , wherein the free magnet has perpendicular magnetization relative to a plane of the apparatus.

18. The apparatus of claim 15 , wherein the free magnet comprises a material comprising one or more of Co, Fe, Ni, or O.

19. The apparatus of claim 15 , wherein the free magnet is one of a paramagnet or a ferromagnet.

20. The apparatus of claim 15 , comprising:

a processor;

a memory coupled to the processor, the memory comprising the bit-line, first and second word- lines, and source-line, magnetic junction, interconnect, and first and second devices; and

a wireless interface to allow the processor to communicate with another device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2018
From: GOSAVI, TANAY; LIN, CHIA-CHING; MANIPATRUNI, SASIKANTH; YOUNG, IAN
To: INTEL CORPORATION
Reel/Frame 046316/0279 →
Continuity (1)
Related Publication 20190386203A1 · Dec 19, 2019